Resistance-changing function body, memory element, manufacturing method therefor, memory device, semiconductor device and electronic equipment

ABSTRACT

A memory function body  113 , which includes a plurality of silver particles  103  covered with silver oxide  104 , is interposed between a first electrode  300  and a second electrode  411 . A magnitude of a current through the memory function body  113  changes on applying a prescribed voltage between the first electrode  300  and the second electrode  411 , and a storage state is discriminated according to the magnitude of the current. The silver particles  103 , which capture electric charges, are covered with the silver oxide  104  that serves as a barrier against the passage of electric charges, and therefore, the memory function body  113  can stably retain electric charges at the normal temperature.

This Nonprovisional application claims priority under 35 U.S.C. §119(a)on patent application Ser. No. P2003-067656 filed in Japan on Mar. 13,2003, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a resistance-changing function body, amemory element, a manufacturing method therefor, a memory device, asemiconductor device and an electronic equipment.

In recent years, it has been proposed to constitute ultramicroelectronic equipment of, for example, a single-electron transistor, asingle-electron memory and the like by employing a memory that includesa nanometer-size particle called the nanodot and nanocrystal in a gateinsulation film. The memory and electronic equipment of this kind areexpected to operate with low power consumption taking advantage of aquantum size effect of Coulomb blockade phenomenon or the like.

FIG. 35 is a view showing a conventional memory that employs particlesin its floating gate. This memory is provided with an oxide film 4802that has a thickness of 2 nm and is formed by thermal oxidation, siliconparticles 4803 that have a particle diameter of 5 nm and are formed onthe oxide film 4802, an oxide film 4804 formed so as to cover thesilicon particles and a polysilicon layer 4805 that serves as a gateelectrode on a channel region located between source and drain regions4806 formed in a p-type silicon substrate 4801.

As a manufacturing method of a memory as shown in FIG. 35, there isproposed a method for depositing amorphous silicon on the siliconthermal oxidation film 4802 by an LPCVD (Low-Pressure Chemical VaporDeposition) apparatus, thereafter forming the silicon particles 4803through an annealing process and further depositing the silicon oxidefilm 4804 on the silicon particles 4803 by a CVD (Chemical VaporDeposition) method (refer to, for example, Japanese Unexamined PatentApplication No. 2000-22005).

As another method for forming particles of the silicon particles 4803 orthe like, there are proposed a method for forming crystals on asubstrate by using CVD, vapor deposition, MBE (Molecular Beam Epitaxy)or the like and a method for forming a thin film and thereafter using afine processing technique of photolithography, etching and the likebesides the use of LPCVD and annealing. According to the methodsdescribed above, the aforementioned particles are formed, andthereafter, an insulator layer like the silicon oxide film 4804 of FIG.35 is laminated on the particles.

However, it is difficult to integrate the conventional memory,single-electron transistor, single-electron memory and so on since theyrequire very fine processing in order to produce a nanosize dot capableof storing one or several electrons and to detect the flow of severalelectrons. Moreover, it is required to make the memory or the like havean extremely low temperature in many cases in order to restrain theoccurrence of malfunction due to thermal fluctuation. Therefore, thememory and the like, which utilize the Coulomb blockade phenomenon orthe like, lack practicability and stay at the experiment level.

Moreover, it is often the case where the aforementioned conventionalmemory manufacturing method has insufficient surface density ofparticles and insufficient miniaturization of particle size. As aresult, there are the disadvantages that the memory window (hysteresis)becomes narrow, a variation in the density is increased and the dataretention characteristic is poor.

In particular, to increase the surface density of the particles by themethod of forming the particles by using the CVD, deposition, MBE and soon, the particles can be formed only on one surface through one-timeprocess in order to raise the surface density of the particles, andtherefore, a similar process is required to be repeated many times.

Moreover, it is extremely difficult to reduce a the particle size andthe distance between particles to the nanometer order at the same timeby the method of using the fine processing technique ofphotolithography, etching and the like after the formation of the thinfilm.

SUMMARY OF THE INVENTION

Accordingly, the object of the present invention is to provide a memorycapable of obtaining a sufficient particle surface density, asufficiently reduced particle size, high practicability withsatisfactory data retention characteristic and comparatively easyintegration and a manufacturing method capable of manufacturing thememory with satisfactory productivity.

In order to achieve the above object, the present invention provides aresistance-changing function body comprising:

-   -   a first electrode;    -   a second electrode;    -   a medium made of a first material interposed between the first        electrode and the second electrode; and    -   at least one conductive particle made of a third material,        having a surface covered with a second material and included in        the medium, wherein    -   the second material has a barrier against passage of electric        charges,    -   the third material has a capability to retain electric charges,        and    -   an electrical resistance between the first electrode and the        second electrode is changed depending on an amount of electric        charges accumulated in the particle.

According to the resistance-changing function body of theabove-mentioned construction, the conductive particle is included in themedium made of the first material. The conductive particle is made ofthe third material and of which the surface is covered with the secondmaterial. The second material has the barrier against the passage ofelectric charges, and the third material has a capability of retainingelectric charges. In this case, the above-mentioned particle is coveredwith the second material, and therefore, the retainment of electriccharges is effectively achieved at the normal temperature. As a result,the magnitude of the current that flows through the medium including theconductive particles covered with the second material changes byapplication of a prescribed voltage between the first electrode and thesecond electrode at the normal temperature. Therefore, the magnitude ofthe current that flows between the electrodes can be changed byelectrical control with a comparatively low voltage at the normaltemperature. Therefore, this resistance-changing function body haspracticability.

Moreover, according to the resistance-changing function body of theabove-mentioned structure, it is also possible to effectively use theCoulomb blockade effect for retaining electric charges at the normaltemperature.

Any material can be employed for the second material so long as thematerial serves as a barrier against electric charges. It is possible toemploy, for example, an insulator. It is possible to employ even a metalor a semiconductor in which a depletion layer is formed like a pnjunction or a Schottky barrier or the like is formed. From a differentviewpoint, the first, second and third materials are only required tosatisfy the condition that electric charges locally exist at or in thevicinity of the particle.

In one embodiment, the first material and the second material aremutually different insulative substances,

-   -   the third material is a conductive material, and    -   the second material is an insulative substance formed by using        the third material.

According to the resistance-changing function body of theabove-mentioned embodiment, the third material is a conductivesubstance, which is therefore able to easily retain electric charges.Moreover, the second material is an insulative substance, which istherefore able to effectively restrain the leak of electric charges fromthe particle. Moreover, the second material is formed of the thirdmaterial, which therefore has a satisfactory congeniality to theparticle constructed of the third material and is able to obtain asatisfactory insulative effect. Therefore, a resistance-changingfunction body of stable characteristics can be obtained.

A memory element of the present invention comprising:

-   -   a first electrode;    -   a second electrode; and    -   a memory function body interposed between the first electrode        and the second electrode, wherein    -   the memory function body includes:    -   a first insulator; and    -   a conductive particle included in the first insulator and having        a surface covered with a material having a barrier against        passage of electric charges, and wherein    -   a magnitude of a current through the memory function body        changes by application of a prescribed voltage between the first        electrode and the second electrode, and a storage state is        discriminated according to the magnitude of the current.

As the material having a barrier against the passage of electriccharges, it is possible to use, for example, an insulator. It ispossible to employ as the material even a metal or a semiconductor inwhich a depletion layer is formed like a pn junction or a Schottkybarrier or the like is formed. From a different viewpoint, the firstinsulator, the particle and the material are only required to satisfythe condition that electric charges locally exist at or in the vicinityof the particle.

In the present specification provided herein, the “conductive particle”indicates that the particle itself has conductivity. Therefore, the“conductive particle” also includes those which are constructed of ametal or a semiconductor and further includes those constructed of anorganic substance so long as they have conductivity. Moreover, the“conductive particle” indicates that the particle has a particlediameter smaller than 1 μm.

As an “storage state” of the memory, there can be enumerated, forexample, a written state corresponding to a logic 1 and an erased statecorresponding to a logic 0.

According to the memory element of the present invention, the magnitudeof the current that flows through the memory function body changes byapplication of the prescribed voltage between the first electrode andthe second electrode by virtue of the conductive particle contained inthe first insulator. That is, by applying the prescribed voltage (forwrite or erase) between the first electrode and the second electrode forthe flow of the current through the memory function body, the magnitudeof the current that flows through the memory function body is changed.When the prescribed voltage (for read) is applied between the firstelectrode and the second electrode, the storage state is discriminatedaccording to the magnitude of the current that flows through the memoryfunction body. In the memory function body, the surface of theconductive particle is covered with the material that has a barrieragainst the passage of electric charges. With this arrangement, themagnitude of the current that flows through the memory function body canbe changed by electrical control with a comparatively low voltage at thenormal temperature. Therefore, this memory element has practicability.

Moreover, it is preferred that the first insulator is constructed ofsilicon oxide and the conductive particle is constructed of asemiconductor or a metal. In this case, the memory element can befabricated by the existing apparatus used in the semiconductor industry.

A memory device of the present invention comprising a memory cellincluding:

-   -   the aforementioned memory element; and    -   a rectifying function body having a rectification effect so as        to determine a direction of the current through the memory        function body of the memory element, wherein    -   the memory element and the rectifying function body are        electrically connected in series to each other.

According to the memory device of the above-mentioned construction, thedirection of the current that flows through the memory function body islimited to one direction by the rectifying function body. Thisarrangement is able to prevent a useless current from flowing throughthe nonselected memory cell by means of the rectifying function bodywhen a plurality of memory cells each of which includes theaforementioned memory function body are arranged in a matrix form and itis attempted to select and operate a specified memory cell from amongthe cells. Therefore, the memory cell selection is facilitated.

Moreover, the rectifying function body should preferably have a Schottkyjunction. This Schottky junction can be fabricated by a junction of ametal and a semiconductor. Therefore, the junction can easily bemanufactured by the existing semiconductor apparatus and is excellent inproductivity.

Moreover, the rectifying function body should preferably have a pnjunction. This pn junction can be constructed of a semiconductor.Therefore, the junction can easily be manufactured by the existingsemiconductor apparatus, thus the rectifying function body is excellentin productivity. Moreover, since the characteristics of the junction caneasily be changed by adjusting the impurity concentrations of the p-typesemiconductor and the n-type semiconductor, the rectifying function bodyis excellent in versatility.

Moreover, the rectifying function body should preferably be providedwith a junction that has a rectification effect, and at least one of thesubstances that constitute this junction should preferably be made ofcontinuous grain boundary silicon. In this case, there is no need forsuch a high temperature as in epitaxial growth in order to form theabove-mentioned junction. Moreover, since the crystallinity is betterthan that of normal polysilicon, it becomes possible to increase themobility and achieve high-speed operation.

A memory device of the present invention comprising a memory cellincluding:

-   -   the aforementioned memory element; and    -   a select transistor for selecting the memory element, wherein    -   the memory element and the select transistor are electrically        connected in series to each other.

According to the memory device of the above-mentioned construction, amemory element which includes the aforementioned memory function bodycan be selected or nonselected by turning on or off the selecttransistor. Moreover, since the current can be prevented from flowingthrough the memory function body by turning off the select transistor,it is possible to prevent changing the facility in flowing the currentthrough the memory function body. Therefore, a stable memory functioncan be maintained for a long time.

Moreover, it is preferable to provide a element for applying a voltagefor destroying the first insulator of the memory function body. Thismemory device is used as a so-called fuse memory by destroying the firstinsulator of the memory function body. In this memory device, it becomespossible to execute write at a low voltage dissimilarly to theconventional fuse memory that employs an insulator containing noparticle as a fuse.

Moreover, it is acceptable to constitute a random-access memory byarranging the aforementioned memory devices in a matrix form. In thiscase, since the structure becomes simple dissimilarly to the floatinggate type memory, the structure is suitable for high integration andexcellent in productivity.

A memory device of the present invention comprising at least two memorycells each including the aforementioned memory element, wherein

-   -   the first insulators of the memory function bodies of the two        memory cells are integrally continuously formed, and    -   the first electrode of one memory cell of the two memory cells        and the first electrode of the other memory cell are        electrically connected to each other, and the second electrode        of the one memory cell and the second electrode of the other        memory cell are electrically isolated from each other.

According to the memory device of the above-mentioned construction, thefirst insulators of the memory function bodies of the two memory cellsare integrally continuously formed. Moreover, the first electrode of onememory cell and the first electrode of the other memory cell of the twomemory cells are electrically connected to each other. Therefore, noisolation region is required to be formed in comparison with the casewhere two memory cells are independently formed, and therefore, theoccupation area of the memory cells can be reduced. Since the secondelectrode of the one memory cell and the second electrode of the othermemory cell are electrically isolated from each other, the two memorycells can operate independently of each other.

A memory device of the present invention comprising:

-   -   at least five memory cells each including the aforementioned        memory element;    -   bit lines extended in a direction of column;    -   source lines extended in a direction of column; and    -   word lines extended in a direction of row, wherein    -   each of the memory cells includes:    -   a select transistor for selecting the memory element; and    -   a rectifying function body for determining a direction of the        current through the memory function body of the memory element,        and wherein    -   each of the memory cells is connected between the bit line and        the source line, and the select transistor of each of the memory        cells is controlled by the word line,    -   with respect to a first memory cell of the five memory cells, a        second and a fourth memory cells are arranged mutually        adjacently in the direction of row, and a third and a fifth        memory cells are arranged mutually adjacently in the direction        of column,    -   the first memory cell and the second memory cell have a shared        bit line, a shared word line and an unshared source line,    -   the first memory cell and the third memory cell have a shared        bit line, a shared source line and an unshared word line,    -   the first memory cell and the fourth memory cell have a shared        source line, a shared word line and an unshared bit line,    -   the first memory cell and the fifth memory cell have a shared        word line,    -   a source line of the first memory cell and a bit line of the        fifth memory cell are shared, and    -   a bit line of the first memory cell and a source line of the        fifth memory cell are shared.

According to the memory device of the above-mentioned construction, theword line, the bit line and the source line can be largely shared, andthe interconnections can be reduced. Therefore, a reduction in theoccupation area of the lines becomes possible.

Moreover, it is preferred that two memory function bodies are laminatedin the direction perpendicular to a substrate. In this case, since thememory cells are three-dimensionally integrated, it is possible toeffectively reduce a total area of the memory cells and increase thememory capacity.

In one embodiment, at least two memory cells are arranged in a directionparallel to a substrate, and the first insulators of the memory functionbodies of the memory cells mutually adjacent in the direction parallelto the substrate are integrally continuously formed.

According to the memory device of the above-mentioned embodiment, thefirst insulators of the memory function bodies are integrallycontinuously formed. Accordingly, the process of separating the memoryfunction body of every cell can be eliminated, and therefore, theproductivity is improved.

In one embodiment, at least two memory cells are arranged in a directionparallel to a substrate, and

-   -   the first insulators and/or the rectifying function bodies of        the memory cells mutually adjacent in the direction parallel to        the substrate are integrally continuously formed.

According to the memory device of the above-mentioned embodiment, theprocess of separating the first insulator and/or the rectifying functionbody of the memory cell can be eliminated, and therefore, theproductivity is improved.

In one embodiment of the memory element, further comprising a thirdelectrode adjacent to the memory function body, wherein

-   -   the third electrode is able to apply a voltage to the memory        function body in a position between the first electrode and the        second electrode in a direction opposing the first electrode and        the second electrode to each other.

Herein, the arrangement that the third electrode is “adjacent” to thememory function body includes the case where the third electrode is indirect contact with the memory function body and the case where thecontact is made via an insulation film.

The present inventor conducted experiments and discovered the fact that,when a voltage was applied to the memory function body in a positionlocated between the first electrode and the second electrode in thedirection in which the first electrode and the second electrode wereopposed to each other by the third electrode, the magnitude of thecurrent through the memory function body grew larger. That is, the widthof the memory window (hysteresis) is increased, and the memory functionis improved. Therefore, according to the memory element of thisembodiment, read errors in reading the storage state are reduced, andthe reliability of the memory element is improved. So long as a voltagecan be applied to the memory function body in the position between thefirst electrode and the second electrode in the direction in which thefirst electrode and the second electrode are opposed to each other, itis acceptable to adopt any arrangement such as an arrangement that thethird electrode is directed in, for example, the direction in which thefirst electrode and the second electrode are opposed to each other.

In one embodiment of the memory element, the first electrode and thesecond electrode are each formed on a surface of a semiconductorsubstrate,

-   -   the memory function body is formed in a region located between        the electrodes on the surface of the semiconductor substrate,        and    -   the third electrode is provided on the memory function body.

According to the memory element of the above-mentioned embodiment, thestructure is roughly equivalent to a structure in which the memoryfunction body is integrated in the channel portion of a MOS typetransistor. In this case, since the structure bears a close resemblanceto that of a logic transistor, the manufacturing is facilitated.Moreover, it becomes easy to consolidate the memory with a logiccircuit.

In one embodiment of the memory element, the first electrode and thesecond electrode are each made of a conductor formed on a substrate,

-   -   the memory function body is formed in a region interposed        between the conductors, and    -   the third electrode is provided on the memory function body.

According to the memory element of the above-mentioned embodiment, thestructure is approximately equivalent to a structure in which the memoryfunction body is integrated into the insulation film portion of a MOStype transistor with a stacked diffusion layer lacking the source, drainand channel. In this case, since the structure bears a close resemblanceto a logic transistor, the manufacturing is facilitated. Moreover, itbecomes easy to consolidate the memory element with a logic circuit.Moreover, it is also possible to form the memory function body on aglass substrate.

It is acceptable to constitute a random-access memory by arranging theaforementioned memory elements in a matrix form. In this case, thestructure, which is simple dissimilarly to the floating gate typememory, is therefore suitable for high integration and excellent inproductivity. Moreover, there can be provided a compact random-accessmemory that allows low-voltage operation.

A memory device of the present invention comprising:

-   -   at least two memory cells each including the aforementioned        memory element, wherein    -   the memory cells are formed on a substrate, and    -   the memory function bodies of the memory cells are laminated in        a direction perpendicular to the substrate.

According to the memory device of the above-mentioned construction, atleast two memory function bodies are laminated in the directionperpendicular to the substrate and three-dimensionally integrated.Therefore, it is possible to considerably reduce the occupation area ofthe memory cells and increase the memory capacity.

A method for manufacturing the aforementioned memory element comprisingthe step of:

-   -   implanting a substance for forming the conductive particle in        the first insulator by a negative ion implantation method.

According to the method for manufacturing the memory element of theabove-mentioned construction, the conductive particle can be formed inthe first insulator by one-time negative ion implantation. Therefore,the memory element can be fabricated with good productivity.

As a method for forming the conductive particle in the first insulator,there can be considered a method for depositing a conductive substanceby the CVD (Chemical Vapor Deposition) method, the deposition method,the MBE (Molecular Beam Epitaxy) method and so on and carrying out heattreatment to form the conductive particle. Another method for formingthe conductive particle in the first insulator, there can be considereda method for depositing a conductive thin film and using fine processingtechniques of photolithography, etching and so on. However, productivityis not satisfactory according to these methods. In contrast to this,according to the ion implantation, the conductive particle can be formedin the first insulator through one-time processing. Furthermore,according to the ion implantation, the fine processing techniques ofphotolithography, etching and so on are not required for the formationof the conductive particle. Therefore, the ion implantation is excellentin productivity.

Moreover, the substance for forming the conductive particle is implantedinto the first insulator by the negative ion implantation method.Therefore, the first insulator and the substrate that supports theinsulator can be prevented from being electrically charged during theimplantation. Therefore, the implantation energy can be accuratelycontrolled, thus a variation of a implantation profile can berestrained. Moreover, since the electrical charge is restrained, it ispossible to restrain the occurrence of a defect caused by the breakdownof a part of the first insulator due to the electrical charge. As aresult of these factors, the reliability of the fabricated memoryelement is improved.

A semiconductor device of the present invention comprises theaforementioned memory element.

According to the semiconductor device of the above-mentionedconstruction, the area of the memory element can be reduced. Therefore,the occupation area of the memory element in the semiconductor devicecan be reduced, thus, the semiconductor device can be constructedcompact in comparison with the conventional case. Since theaforementioned memory element can operate with a comparatively lowvoltage. Therefore, a power source can be shared by a memory circuitthat includes such a memory element and a logic circuit or the like, andthis facilitates the consolidation of the memory circuit with the logiccircuit. As a result, reduced power consumption becomes possible.

Electronic equipment of the present invention comprises theaforementioned semiconductor device.

According to the electronic equipment of the above-mentionedconstruction, the semiconductor device is constructed compact, and thisequipment can be consequently made compact. Moreover, since thesemiconductor device has low power consumption, the operating life ofthe battery mounted in this equipment is protracted. Therefore, thiselectronic equipment is suitable for portable use.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingswhich are given by way of illustration only, and thus are not limitativeof the present invention, and wherein:

FIG. 1 is a view schematically showing the cross section of aresistance-changing function body of one embodiment of the presentinvention;

FIGS. 2A through 2D are views for explaining the fabrication processesof the resistance-changing function body of FIG. 1; FIG. 2E is anenlarged view of part of FIG. 2D;

FIG. 3 is a graph showing results of measuring a current-to-voltage(I–V) characteristic of the resistance-changing function body of FIG. 1;

FIG. 4 is a view showing a memory element formed by employing theresistance-changing function body of FIG. 1;

FIG. 5 is a graph for explaining the memory operation of the memoryelement of FIG. 4;

FIG. 6A is a view schematically showing a memory device including amemory element and a select transistor; FIGS. 6B through 6D are viewsshowing its concrete constructions;

FIG. 7 is a diagram illustrating a memory device provided with memorycells that include the aforementioned memory element and a selecttransistor, which are arranged in a matrix form;

FIG. 8 is a diagram illustrating a memory device provided with memorycells that include the aforementioned memory element and a selecttransistor, which are arranged in a matrix form;

FIG. 9A is a view showing the cross-sectional structure of a memorydevice provided with memory cells that include the aforementioned memoryelement and a select transistor; FIG. 9B is a view showing the portionthat substantially performs memory operation in the memory function bodyof FIG. 9A;

FIGS. 10A and 10B are views showing the cross-sectional structure of amemory device that includes the aforementioned memory element and aselect transistor; FIG. 10C is a view showing the portion thatsubstantially performs memory operation in the memory function body ofFIG. 10A;

FIG. 11 is diagram illustrating a memory device provided with memorycells that include the aforementioned memory element and a rectifyingfunction body, which are arranged in a matrix form;

FIG. 12A is a view schematically showing a memory cell that includes theaforementioned memory element and a rectifying function body constructedof a pn junction; FIGS. 12B through 12E are views showing its concreteconstructions;

FIG. 13A is a view schematically showing a structure whose constituentelements are shared by mutually adjacent two memory cells that includesa memory element and a rectifying function body constructed of a pnjunction in each of the memory cells; FIGS. 13B through 13D are viewsshowing its concrete constructions;

FIG. 14 is a diagram illustrating a memory device provided with memorycells that include the aforementioned memory element, the rectifyingfunction body and a select transistor, which are arranged in a matrixform;

FIG. 15A is a view schematically showing a memory cell that includes theaforementioned memory element and a rectifying function body constructedof a Schottky junction; FIGS. 15B through 15E are views showing itsconcrete constructions;

FIG. 16A is a view schematically showing the structure whose constituentelements are shared by mutually adjacent two memory cells that include amemory element and a rectifying function body constructed of a Schottkyjunction in each memory cell; FIGS. 16B through 16D are views showingits concrete constructions;

FIG. 17A is a view showing the three-dimensional spatial structure of amemory device in which a plurality of aforementioned memory elements arearranged in a direction perpendicular to a substrate; FIG. 17B is a viewshowing electrical connection of the constituent elements in FIG. 17A;

FIG. 18A is a view showing the three-dimensional spatial structure of amemory device in which a plurality of aforementioned memory elements andrectification function bodies are arranged in a direction perpendicularto the substrate; FIG. 18C is a view showing the electrical connectionof the constituent elements in FIG. 18A; FIG. 18B is a view showing amodification example of the structure of FIG. 18A; FIG. 18D is a viewshowing the electrical connection of the constituent elements in FIG.18C;

FIGS. 19A through 19J are views for explaining the fabrication method ofthe memory device that has the three-dimensional spatial structure ofthe type shown in FIG. 18A;

FIGS. 20A and 20B are views for explaining the regions that performmemory operation in a memory function body layer;

FIGS. 21A through 21J are views for explaining a fabrication method forforming a memory device that has a three-dimensional spatial structureinto a state in which they are integrally continuous in the layerlaminating direction;

FIGS. 22A and 22B are views showing modification examples of thestructure shown in FIGS. 21E and 21J;

FIGS. 23A and 23B are views showing modification examples of thestructure shown in FIGS. 22A and 22B;

FIGS. 24A and 24B are views showing modification examples of thestructure shown in FIGS. 23A and 23B;

FIG. 25A is a view showing the current path of the structure shown inFIGS. 23A and 23B; FIG. 25B is a view showing the current path of thestructure shown in FIGS. 24A and 24B;

FIG. 26A is a view showing the schematic cross section of a memoryelement of one embodiment of the present invention; FIG. 26B is a viewshowing an example whose electrode arrangement is different from that ofFIG. 26A;

FIGS. 27A through 27E are views for explaining the fabrication method ofa memory element that has the electrode arrangement of the type of FIG.26B;

FIGS. 28A through 28E are views for explaining another fabricationmethod of a memory element that has the electrode arrangement of thetype of FIG. 26B;

FIG. 29A is a view showing a plan layout of a memory device integratedthree-dimensionally; FIG. 29B is a view taken along the line and shownby arrows B—B′ in FIG. 29A;

FIGS. 30A through 30E are views showing the cross sections in thefabrication processes of the memory device of FIG. 29;

FIGS. 31A through 31F are views showing a plan layout in the fabricationprocesses of the memory device of FIG. 29;

FIG. 32A is a view showing a memory device structure in which theinterconnections connected to the first, second and third electrodes aresubstantially perpendicular to one another; FIGS. 32B, 32C and 32D areviews showing the memory of FIG. 32A viewed from the direction of B, thedirection of C and the direction of D, respectively;

FIG. 33A is a view showing the plan layout of a semiconductor device ofone embodiment of this invention; FIG. 33B is a view showing the planlayout of a conventional semiconductor device;

FIG. 34 is a view showing a portable telephone as one example of theelectronic equipment of this invention; and

FIG. 35 is a view showing a conventional memory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail below on the basis ofthe embodiments shown in the drawings.

FIG. 1 is a schematic sectional view showing the resistance-changingfunction body of one embodiment of the present invention. Thisresistance-changing function body 100 is provided with a first electrode111, a second electrode 112 and an insulator 101 that serves as a mediuminterposed between this first electrode 111 and the second electrode112. One or more conductive particles 103, each of which has a nanometersize and a surface covered with an insulator 104, are contained in theinsulator 101.

The resistance-changing function body 100 is fabricated in a manner asshown in the process charts of FIGS. 2A through 2D.

This embodiment employs silicon oxide as a first material for thematerial of the insulator 101, uses silver as a third material for thematerial of the particles 103 and uses silver oxide as a second materialfor the material of the insulator 104 so as to be manufacturable byusing the existing apparatuses used in the semiconductor industry.

First of all, as shown in FIG. 2A, a silicon oxide film 101 is formed inthe surface portion of a silicon substrate 300 by a thermal oxidationprocess. In this example, the silicon oxide film 101 is formed to a filmthickness of about 35 nm. It is to be noted that the silicon portionother than the silicon oxide film 101 of the substrate 300 is used as asecond electrode.

Next, as shown in FIG. 2B, silver 303 is introduced into the siliconoxide film 101 by the negative ion implantation method.

In this case, if implantation energy is excessive, then a range ofdistribution of the implanted silver 303 in the silicon oxide film 101becomes to broad, and this is improper to the resistance change functionand exerts excessive damage to the silicon oxide film 101,disadvantageously causing a defect. Therefore, the implantation energyshould preferably be smaller than 100 keV and more preferably beespecially set smaller than 50 keV.

Moreover, if the dosage of silver (dosage per unit area) is extremelylarge, then the particle diameter of the conductive particle becomesextremely large, and the damage to the silicon oxide film 101 isincreased. If the dosage is extremely small, the distribution density ofthe conductive particles becomes extremely small. Therefore, the dosageof silver should preferably be greater than 1×10¹²/cm² and smaller than1×10²⁰/cm² and set, for example, greater than 1×10¹⁴/cm² and smallerthan 1×10¹⁷/cm².

In the present embodiment, the implantation energy was set to about 15keV, and the dosage was set to about 1×10¹⁵/cm². It is a matter ofcourse that the implantation energy and the dosage to be selected differdepending on the kind of ions to be implanted.

Moreover, the present embodiment adopts the negative ion implantationmethod as an ion implantation method. According to this implantationusing negative ions, there is no possibility of the rise of the surfacepotential of the material (silicon oxide film 101 in the presentembodiment) that undergoes the implantation to a potential close to theacceleration voltage of positive ions dissimilarly to the case wherepositive ions are used, so that the surface potential of the siliconoxide film 101 can be suppressed to a very low value of about severalvolts. More in detail, when the positive ion implantation is used,secondary electrons of negative charges are discharged when the ions ofthe positive charges are injected into the surface of the silicon oxidefilm 101. Therefore, the surface of the silicon oxide film 101 keepsbeing positively charged in accordance with continuing the implantationof the positive ions, and the surface potential eventually rises to theacceleration voltage of the positive ions. In contrast to this,according to the negative ion implantation method, secondary electronsof negative charges are discharged when the ions of negative charges areinjected into the surface of the silicon oxide film 101. Therefore, thesurface potential of the silicon oxide film 101 settles within aboutpositive and negative several volts. As a result, the fluctuation of theeffective acceleration voltage is reduced in comparison with thepositive ion implantation, and therefore, it becomes possible torestrain the variation in the implantation depth of silver. Moreover,since the silicon oxide film 101 that undergoes the implantation and thesilicon portion located below the film are scarcely electricallycharged, it becomes possible to restrain the occurrence of defects dueto dielectric breakdown and the like. In the present embodiment, anegative ion implantation apparatus produced by Nissin Electric CO.,Ltd. was used.

Next, the silicon oxide film 101 is subjected to heat treatment, so thatthe silver implanted in this silicon oxide film 101 is cohered ordiffused. Through this process, silver particles 102 are formed asconductive particles in the silicon oxide film 101 as shown in FIG. 2C.Moreover, the defects, which have occurred in the silicon oxide film 101during the ion implantation, are restored by the heat treatment.

The temperature of heat treatment is not effective when it is extremelylow, but the implanted element (silver) is diffused and melted when itis extremely high. Therefore, particles cannot be formed. Accordingly,the temperature of heat treatment should preferably be set higher than200° C. and lower than the melting point of the implanted element(silver). Moreover, the effect of the heat treatment at theabove-mentioned temperature is increased by being effected for a longtime even at a comparatively low temperature. However, if the time isextremely long, it sometimes occurs the case where the particle diameterof the particles becomes extremely large or the case where the implantedelement diffuses to a region outside the region in which the particlesshould be formed. Therefore, the time to effect the heat treatmentshould preferably be set shorter than 24 hours.

In general, heat treatment is carried out in an inert atmosphere ofargon or the like, whereas the heat treatment of the present embodimentis carried out in an atmosphere for forming an insulator that covers thesurfaces of the silver particles 102. That is, the heat treatment iscarried out in a vapor phase including oxygen, forming the silverparticles 102 in the silicon oxide film 101 and diffusing oxygen in thesilicon oxide film 101. Through this process, silver oxide 104, whichserves as an insulative substance and the second material, is formed inthe surface portions of the silver particles 102. That is, the silveroxide as the second material is an insulative substance formed by usingsilver as the third material.

It is to be noted that the conditions of the temperature, time and theflow rate of vapor phase of the heat treatment differ depending on thematerial to be employed, the particle diameter of the particles to beformed and the thickness of the insulator to be formed on the surface.

In the present embodiment, by carrying out the heat treatment in anoxidizing atmosphere for about several hours at a temperature slightlylower than that of the silicon thermal oxidation condition, there areformed silver particles 103 covered with the silver oxide 104 as shownin FIG. 2D.

It is acceptable to form an insulator constructed of a nitride as thesecond material around the silver particles 103 besides the insulatorconstructed of an oxide. For example, when the conductive particles areformed of silicon, there is a practice to inject silicon as a conductorand thereafter carry out heat treatment in, for example, an ammoniaatmosphere. Through this process, the silicon particles are formed, anda silicon nitride as an insulator is formed in the surface portion ofthe silicon particles.

Moreover, it is acceptable to first carry out the heat treatment in aninert atmospheres of argon, nitrogen or the like in which the conductiveparticles are formed to a certain extent, and thereafter change theatmosphere to an atmosphere in which the conductive particles are partlymade insulative. According to this method, the conductive particles canbe made insulative after the size of the conductive particles isadjusted to the desired size, and therefore, the diameter of theconductive particles can be formed accurately to the desired size. Forexample, when the normal thermal processing furnace is used, a treatmenttemperature of about 300° C. to 900° C. is preferable in the inertatmosphere of argon, nitrogen or the like. For example, the heattreatment is effected for about one hour at a temperature of about 700°C. in the argon atmosphere by means of a ceramics electric tube furnacemade by Asahi Rika, CO., Ltd. This condition of heat treatment is in thecase of the silver particles, and the optimum heat treatment conditiondiffers depending on the material to be formed into the conductiveparticles.

Further, when the heat treatment for forming the conductive particles iscarried out at a comparatively low temperature, it is preferable tosubject the insulation film as the medium to heat treatment at atemperature of about 500 to 1000° C. in order to repair the defectscaused by the implantation. At this time, since an inconvenience of thefusion or diffusion of the conductive particles occurs when the heattreatment is effected for a long time, it is preferable to carry out RTA(Rapid Thermal Annealing), i.e., heat treatment for a short time.

As a method for forming an insulator on the surface of the conductiveparticles, there is a method for carrying out ion implantation ofoxygen, nitrogen or the like and thereafter carrying out oxidation,nitridation or the like by an annealing process besides theaforementioned thermal oxidation in the oxidizing atmosphere and thermalnitridation in the nitriding atmosphere. According to the ionimplantation method, oxygen or nitrogen can be supplied to the desireddepth in comparison with the method by thermal diffusion from thesurface in the thermal processing furnace. Therefore, this method isespecially effective when, for example, it is desired to avoidoxidation, nitridation and so on in the vicinity of the surface of themedium constructed of the first material including conductive particles.

The states of the conductive particles and the insulator produced by themanufacturing method of the present embodiment were examined bycross-sectional TEM (Transmission Electron Microscope) observation. As aresult, as shown in FIG. 2D, it was confirmed that the silver particles103 of a nanometer size of about 2 to 3 nm and the silver oxide 104 thatcovers the periphery of the particles were formed at the prescribeddepth corresponding to the acceleration energy of silver ions. FIG. 2Eis an enlarged view of part of FIG. 2D.

As described above, according to the present embodiment, the negativeion implantation method is used in forming the silver particles 102 inthe silicon oxide film 101. Therefore, silver can easily be implanted tothe desired depth in the silicon oxide film 101 while controlling theelectrification of the silicon oxide film 101. Moreover, the ionimplantation method is used for the formation of the silver particles102. Accordingly, there are fewer processes than when the conductivefilm is etched, and no nanoscale fine processing technique is used,dissimilarly to the conventional case. Therefore, the nanometer-sizeparticles can be formed with satisfactory productivity.

After the silver particles 103 covered with the silver oxide 104 areformed in the silicon oxide film 101, a first electrode 111 is formed onthe silicon oxide film 101. The material of this first electrode 111 maybe either a metal or a semiconductor or an organic substance so long asit has conductivity. As a method for forming the first electrode 111,there can be adopted the CVD (Chemical Vapor Deposition) method, thedeposition method, the MBE (Molecular Beam Epitaxy) method and so on. Inthe present embodiment, the first electrode 111 is formed through Alfilm formation by the normal vacuum deposition method, completing aresistance-changing function body.

According to the resistance-changing function body of the presentembodiment, the silver particles 102 can be formed with a highconcentration through fewer processes within a short time by ionimplantation and heat treatment. According to the ion implantationmethod, no fine processing technique is required for the formation ofthe silver particles 102, and therefore, the resistance-changingfunction body can be manufactured with satisfactory productivity.

Although the silver particles 102 are employed as the conductiveparticles in the present embodiment, it is acceptable to form conductiveparticles by using a conductor of a metal such as gold or copper otherthan silver or a semiconductor such as silicon or germanium. It is to benoted that gold is not easily oxidized, and it is difficult to form aninsulator around the particles after the formation of the particles. Incontrast to this, it is preferable to employ a material of, for example,aluminum, which forms a strong oxide film on its surface throughoxidation. It is also acceptable to form the conductive particles byusing tungsten, niobium, zirconium, titanium, chromium, tin, cobalt,nickel, iron, antimony, lead and so on.

Moreover, the silver particles 102 were formed as the conductiveparticles in the silicon oxide film 101 formed by subjecting the siliconsubstrate to thermal oxidation. However, the silver particles may beformed in another insulator of a glass substrate or the like, asemiconductor substrate and so on.

Moreover, the silicon oxide film is not limited to the thermal oxidationfilm but allowed to be a silicon oxide film formed by the CVD method orthe like or one obtained by oxidizing polysilicon or amorphous silicon.It is to be noted that a silicon oxide film obtained by oxidizingsingle-crystal silicon is more preferable since it has a better filmquality. Furthermore, it is possible to employ another insulator besidesthe silicon series insulators of silicon nitride and so on.

Moreover, in the present embodiment, the material of conductiveparticles is implanted in the medium constructed of the insulativesubstance by the negative ion implantation method. Therefore, it ispossible to effectively restrain the electrification of the insulativemedium and the substrate which supports the insulative medium during theimplantation. Therefore, the implantation depth of the material of theconductive particles can be accurately controlled, and the variation indistribution profile of the material can be restrained. That is, theformation depth and region of the conductive particles can be accuratelycontrolled. Moreover, since the electrification during the implantationis restrained, it is possible to restrain the occurrence of defects as aconsequence of the destruction of the insulative medium due to theelectrification. Consequently, the reliability of theresistance-changing function body can be effectively improved.

FIG. 3 is a graph showing a current-to-voltage (I–V) characteristic atthe normal temperature (25° C.) of the resistance-changing function body100 fabricated by the aforementioned method.

This current-to-voltage characteristic exhibits a change in the currentthat flows through this first electrode 111 when the second electrode112 is grounded and the voltage applied to the first electrode 111 ischanged. First of all, if the application voltage of the first electrode111 is continuously raised from about −1 V, then the absolute value ofthe current reduces as indicated by the arrow S1. Subsequently, if thevoltage is continuously lowered from about 0 V, then the absolute valueof the current value increases as indicated by the arrow S2 through aroute different from the arrow S1. When the application voltage reaches−1 V, the absolute value of the current value lowered as indicated bythe arrow S2 becomes smaller than that of the initial current value whenthe application voltage has started rising from −1 V. The fact that theabsolute value of the current has reduced with respect to the sameapplication voltage means that the resistance has increased. Asdescribed above, hysteresis appears in the current-to-voltage (I–V)characteristic shown in FIG. 3. It can be said that this is because asatisfactory Coulomb blockade is achieved by the mutual isolation of theconductive particles 103 due to a satisfactory barrier effect given fromthe insulator 104 that covers the particles.

Moreover, it can also be considered that the cause of the occurrence ofhysteresis is ascribed to the change of coulombic energy as aconsequence of the diffusion, disappearance or the enlargement throughcohesion of extremely minute particles of the plurality of conductorparticles due to the influence of the current. It can otherwise beconsidered that the coulombic energy has changed as a consequence of thedischarge of electrons from the conductor particles due to thermalenergy caused by Joule heat.

Moreover, the following can be considered as another cause of theoccurrence of hysteresis. That is, one or several electric charges areaccumulated in a specified silver particle 103 out of the plurality ofsilver particles 103 in the silicon oxide film 101, and a Coulombinteraction is exerted on the electrons of the other silver particles103 that form a current path in the vicinity of the specified silverparticle 103 due to the accumulated electric charges. As a result, itcan be considered that the easiness of the flow of the current in thecurrent path, i.e., the electrical resistance changes. It can beconsidered that the aforementioned hysteresis appears due to any one ora combination of a plurality of these effects.

However, there is also a possibility that the hysteresis appears due toa factor other than these. Anyway, it is clear that a sufficiently largehysteresis can be obtained in practice according to the resistancefunction body of the present invention irrespective of the factor.

In the case where an excessive voltage is applied across the first andsecond electrodes 111 and 112 of the resistance-changing function body100, the current value has remarkably increased. It can be consideredthat this is ascribed to the change of the silver particle 103 containedin the silicon oxide film 101. Otherwise, it can be considered that theabove is ascribed to the dielectric breakdown of either one or both ofthe portion of the silicon oxide film 101 and the silver oxide 104located between the silver particles 103 and 103. It is to be noted thatthe portion of the silicon oxide film 101 and the silver oxide 104located between the silver particles 103 and 103, which are tunnelbarriers, therefore scarcely cause dielectric breakdown. Accordingly, itcan be considered that the above is ascribed to the diffusion orcohesion of the silver particles 103 or the change of the silver oxide104 due to Joule heat or the change in the state of the silver particles103 due to migration caused by the current.

If this property is utilized, there occurs a large difference in thechange of the current value between when it is operated with a propervoltage and when an excessive voltage is applied to it. Therefore, oneresistance-changing function body 100 can be operated in more than twomodes.

The resistance-changing function body 100 of the present embodiment isable to be used to discriminate binary data by way of the magnitude ofthe current value which varies due to the aforementioned hysteresiseffect, and is able to be used as a memory function body. That is, thesilicon oxide film 101 including the silver particles 103 and the silveroxide 104 functions as a memory function body 113. Theresistance-changing function body of the present invention, which can beconsidered to have a capability of capturing electrons, can also becalled a charge retention function body.

Conventionally, a fuse memory that has utilized the dielectric breakdownof the insulation film or the like has needed a high voltage for causingthe dielectric breakdown of the insulation film or the like. In contrastto this, the resistance-changing function body 100 of the presentembodiment, when used as a fuse memory, has a comparatively smallthickness of the portion of the silicon oxide film 101 and the silveroxide 104 between the silver particles 103 and 103 corresponding to thesubstantial insulation film thickness, and these insulation films arecapable of producing the tunnel effect. Therefore, it becomes possibleto execute write operation at a voltage lower than in the conventionalfuse memory. Therefore, the present resistance-changing function body100 can also be used as a fuse memory of low-voltage operation.

In the present embodiment, the particle diameter of the silver particle103 was approximately not greater than 3 nm within the range of TEMobservation. Resistance-changing function bodies that had conductiveparticles of a particle diameter of not greater than approximately 6 nmand conductive particles of a particle diameter of not greater thanapproximately 10 nm were fabricated by a manufacturing method similar tothat of the present embodiment, and these resistance-changing functionbodies were subjected to an experiment for measuring the I–Vcharacteristic. As a result, it was discovered that the hysteresis ofthe I–V characteristic became smaller as the particle diameter of theconductive particles increased and the hysteresis had the tendency ofbecoming indistinct even at a temperature lower than the roomtemperature. As a result of experiments of the conductive particles ofother particle diameters, it was clarified that the particle diameter ofthe conductive particle was required to be not greater than 11 nm orpreferably not greater than 7 nm and more preferably not greater than 4nm in order to obtain hysteresis.

In the present specification, the term of “particle diameter” means thesize of the particle, which corresponds to the “diameter” thereof whenthe shape of the particle is approximately spherical or is able to beapproximated to a sphere. In the present invention, the particle shapeshould preferably be close to a spherical shape. However, if a conductorof a particle of a deformed or imperfect shape is employed, it ispossible to regard any one of the diameter of a spherical conductor thathas the same volume as that of the above-mentioned conductor, thediameter of a sphere that has a surface area equivalent to the surfacearea of the above-mentioned conductor, the diameter of a sphere that hasa volume equivalent to the volume of the above-mentioned conductor, anda distance between two points of the particle, the points being mutuallymost apart from each other, as the particle diameter. For example, it ispossible to regard the “semimajor axis” in the case where the shape ofthe particle can be approximated to an elliptical sphere, the cubic rootof the value derived by multiplying semimajor axis by squared semiminoraxis or the like as the particle diameter.

When the Coulomb blockade effect is utilized to retain electric charges,the energy necessary for making the electric charges break away from theconductive particle should be sufficiently greater than the thermalenergy due to the ambient temperature in consideration of the capacityof the conductive particle so that the Coulomb blockade effect becomesremarkable. For the above purpose, the radius of the conductive particleshould be about 0.5 nm to 1 nm when the conductive particle is assumedto be a perfect conductive sphere. The Coulomb blockade effect itselfbecomes more remarkable as the particle diameter of the conductiveparticle becomes smaller. However, a high voltage is needed across thefirst and second electrodes when the particle diameter of the conductiveparticle is extremely small, and therefore, the extremely small particlediameter is not preferable from the viewpoint of device applications.

Moreover, the resistance-changing function body 100 of the presentembodiment undergoes negative ion implantation in order to form thesilver particles 102 in the silicon oxide film 101. Therefore, thesilicon oxide film 101 has kept a quality equivalent to that of thesilicon oxide film before implantation and has become of very highreliability. Moreover, the processing time of the formation of theparticle is reduced in comparison with the case where the conductiveparticle is formed by CVD or the like, and therefore, satisfactoryproductivity is possessed.

Moreover, according to the negative ion implantation, the variation inthe distribution profile of conductive particles due to electrificationcan be restrained as described above. Therefore, the variation in thedistribution profile of the particles 102 in the thickness direction ofthe silicon oxide film 101 can be restrained. Therefore, the siliconoxide film 101 that includes the silver particles 103 and the silveroxide 104, i.e., the memory function body 113 can be formed into a thinfilm and is allowed to be miniaturized. When the memory function body113 is formed into a thin film, the effective electric field applied tothe memory function body 113 becomes stronger than when the memoryfunction body 113 is thick even with the same voltage applied across thefirst and second electrodes 111 and 112. Therefore, if a memory elementis formed of the resistance-changing function body 100, it becomespossible to reduce the operating voltage of this memory element andimprove both productivity and low power consumption.

FIG. 4 is a view showing a memory element 150 that has a structuresimilar to that of the resistance-changing function body and is providedwith an electrode 411 as a first electrode obtained by depositing andpatterning an Al film. That is, the silicon oxide film 101 is the firstinsulator, the silver particles 103 are the conductor particles, and thesilver oxide 104 is the second insulator. A power source and a currentsensor (not shown) are connected to the electrode 411. FIG. 5 is a graphshowing the current-to-voltage (I–V) characteristic at the normaltemperature (25° C.) of a memory element 150 provided with thiselectrode 411. Operation for discriminating the storage state of thememory element 150 will be described by using this graph.

The characteristic of the memory element 150 shown in FIG. 5 is obtainedby grounding the silicon portion of the substrate 300, applying avoltage to the first electrode 411 and observing the current that flowsthrough the first electrode 411 similarly to the case of FIG. 3 of theresistance-changing function body. First of all, if the applicationvoltage of the first electrode 411 is continuously raised from Vw, thenthe current value of the first electrode 411 increases from its initialvalue I_(i) as indicated by the arrow S1. Subsequently, if theapplication voltage of this first electrode 411 is continuously loweredafter the application voltage reaches Ve, then the current value reducesas indicated by arrow S2 through a route different from the arrow S1.When the application voltage is lowered to Vw, there is a resultingcurrent value Ij of which the absolute value is smaller than the initialcurrent value I_(i) when this application voltage is raised. Asdescribed above, the fact that the magnitude of the current has reducedwith respect to the same voltage Vw means that the resistance hasincreased. As described above, hysteresis appears in thecurrent-to-voltage (I–V) characteristic shown in FIG. 5.

In this case, as shown in, for example, FIG. 5, a write voltage Vw andan erase voltage Ve are set. Then, a read voltage Vr for discriminatingthe written state from the erased state is set that the voltage becomesthe central voltage value of the memory window (range of the voltagevalue that causes hysteresis), and a reference current value Ij thatserves as a criterion for discrimination is set. The storage state ofthis memory element 150 can be discriminated by reading the magnitude ofthe current when the read voltage Vr is applied according to therelation of the magnitude between the read value of the current and thereference current value Ij. For example, the state is the erased state(logic 0) when the read value of the current is greater than thereference current value Ij, and the state is the written state (logic 1)when the read value of the current is smaller than the reference currentvalue Ij.

As described above, the memory element 150 that employs the memoryfunction body can be used as a binary memory.

In another embodiment, a conductive particle can be formed of silicon inplace of silver. That is, silicon was implanted by a dosage of 1×10¹⁵ to1×10¹⁶/cm² with implantation energy of 10 to 15 KeV into a siliconthermal oxidation film. Then, heat treatment was carried out in anitriding atmosphere, and a memory function body, in which SiN/Siparticles obtained by covering the surfaces of the silicon particleswith SiN discretely existed in SiO₂, was fabricated. The heat treatmentwas carried out for several hours at a temperature of about 900° C. inan ammonia atmosphere.

The memory function body fabricated in the present embodiment has agreat hysteresis (i.e., the memory window is large) and a satisfactorycharge retention characteristic in comparison with the conventionalmemory function body that has the particles formed by CVD and etching.This is because the insulation film, which includes the SiN/Siparticles, is the silicon thermal oxidation film and therefore has aquality better than that of the conventional CVD film and polysiliconoxide film. Furthermore, there is an influence that the silicon particlesurface is covered with SiN and this SiN has a good quality with anapproximately uniformly formed thickness obtained through an annealingprocess.

Moreover, in another embodiment, a conductive particle is formed ofaluminum in place of silver. The above-mentioned aluminum is implantedinto a silicon thermal oxidation film by a dosage of 1×10¹⁴ to1×10¹⁶/cm² with implantation energy of 5 to 15 KeV. Then, heat treatmentis carried out at a temperature of not higher than 600° C. Through thisprocess, there was fabricated a memory function body, in which Al₂O₃/Alparticles obtained by covering the surfaces of aluminum particles withalumina discretely existed in SiO₂.

The memory function body of the present embodiment has a greaterhysteresis (i.e., the memory window is large) and a better chargeretention characteristic than those of the conventional memory functionbody. This is because an excellent charge storage capability can beobtained by the use of aluminum that is a metal used as conductiveparticles and further because an excellent charge retention capabilitycan be obtained by surrounding the conductive particles with aluminathat is a satisfactory insulator. The above-mentioned alumina is in aso-called passive state, and the oxidation thereof scarcely progressesafter being formed by the oxidation of the aluminum particle surface.Therefore, the above-mentioned alumina is formed approximately uniformlyin thickness. With this arrangement, there can be provided a memoryfunction body that has stable memory operation and high reliability.

In another embodiment, the particle contained in the memory functionbody is formed by another method. That is, a diffusion method is used asa method for adding a material for forming conductive particles into thefirst insulator instead of the ion implantation method. For example,when an aluminum particle is formed in a silicon thermal oxidation filmsimilarly to the aforementioned embodiment, firstly, a silicon thermaloxidation film is formed similarly to the aforementioned embodiment.Thereafter, an aluminum film is formed on the silicon thermal oxidationfilm by means of a vacuum evaporation system. It is acceptable to use asputtering method instead of the deposition method and use any method solong as the aluminum film can be formed.

Subsequently, heat treatment is carried out at a temperature of about400° C. to 600° C., diffusing aluminum in the silicon thermal oxidationfilm. Subsequently, heat treatment is carried out at a temperature lowerthan the temperature of diffusion, and thereafter oxidation is carriedout to form alumina as a second insulator.

Subsequently, an electrode is formed similarly to the aforementionedembodiment, forming a memory function body. It was confirmed that thismemory function body had a satisfactory memory characteristic similarlyto the embodiment in which the aluminum particles were formed byimplantation.

Since the memory function body of the present embodiment uses thediffusion method, the memory function body of the present invention canbe fabricated more simply.

It is preferable to employ a silicon film that contains Al in place ofthe aluminum film formed on the silicon thermal oxidation film becausethe aluminum concentration in the vicinity of the surface of the siliconthermal oxidation film can be prevented from increasing. Furthermore, itis more preferable to employ a material such that the oxide forms apassive state, as represented by aluminum because an insulator of goodquality can be formed by oxidation around the conductive particles.

In the present embodiment, the memory element can be fabricated by theexisting semiconductor apparatuses without using any special fineprocessing technique. Moreover, it is, of course, possible to fabricateonly one particle by using a fine processing technique of electron beamor the like as in the single-electron transistor proposed in recentyears.

Moreover, it is preferable to carry out a hydrogen sintering process informing the conductive particles because the unnecessary interface stateand so on can be restrained to allow a resistance-changing function bodyand a memory function body of stable operation to be obtained.

FIG. 6A is a schematic sectional view showing a memory device accordingto an embodiment of the present invention. In this memory device, amemory element including a memory function body 604 (which has the samestructure as that of the memory function body 113 of the embodiment ofFIG. 1) and a select transistor 601 for selecting the memory elementincluding the memory function body 604 are electrically connected inseries to each other and integrated on a silicon substrate 600. Theselect transistor 601 is a normal MOS transistor and includes a drainregion 602 and a source region 603, which are formed mutually apart onthe surface of the silicon substrate 600, a gate oxide film 608 thatcovers the substrate surface between the regions and a gate electrode609. It is to be noted that contacts 605 and 606 are connected to thedrain region 602 and the source region 603, respectively.

In this example, the memory function body 604 is provided as part of thecontact 605 connected to the drain 602 of the select transistor 601. Inconcrete, FIG. 6B shows an example in which the memory function body 604is provided so as to be in contact with the drain region 602. FIG. 6Cshows an example in which the memory function body 604 is provided incontact with a metal interconnection of a bit line 626. FIG. 6D shows anexample in which the memory function body 604 is provided partway in thecontact 605.

FIG. 7 shows a memory device provided with memory cells M each of whichincludes the aforementioned memory element and the select transistor,the memory cells being arranged in a matrix form. Word lines W and bitlines B are extended in the direction of row and in the direction ofcolumn, respectively. The memory function body 604 of the memory elementand the select transistor 601 of each of the memory cells M areconnected in series between the corresponding bit line B and the ground.

For example, in selecting the memory cell M(320), a voltage VH higherthan the threshold voltage of the select transistor is applied to theword line W(300) connected to the memory cell, and a voltage of 0 V(ground potential) is applied to the other word lines W(100), W(200) andW(400). In addition, a voltage Vb necessary for write, read and erase isapplied to the bit line B(020) connected to the memory cell M(320).Meanwhile, a voltage of, for example, 0 V, which causes neither writenor erase operation even if the select transistor is in the on-state, isgiven to the other bit lines B(010), B(030) and B(040).

By the above operation, a voltage of a potential difference of about Vbis applied to the memory function body 604 of the memory cell M(320),performing the memory operation. In the other memory cells, since theselect transistor 601 is in the off-state or the potential of the bitline B is 0 V even if the select transistor 601 is in the on-state, novoltage is applied to the memory function body, performing no memoryoperation.

FIG. 8 shows a memory device provided with memory cells each of whichincludes the aforementioned memory function body 604 of the memoryelement and the select transistor 601, the memory cells being arrangedin a matrix form. In this example, the arrangement of the memoryfunction body 604 and the select transistor 601 are symmetrical(inverted) between memory cells that are mutually adjacent in thedirection of row, and the memory function body 604 and the selecttransistor 601 of each of the memory cells are connected in seriesbetween the corresponding bit line and source line.

For example, in selecting the memory cell M(320), a voltage VH higherthan the threshold voltage of the select transistor is applied to theword line W(300) connected to the memory cell, and a voltage of 0V(ground potential) is applied to the other word lines W(100), W(200) andW(400). In addition, a voltage Vb necessary for write, read and erase isapplied to the bit line B(020) connected to the memory cell M(320).Meanwhile, a voltage of, for example, Vb, which causes neither write norerase operation of the memory cell M(310), is applied to the source lineS(010). A voltage of, for example, 0 V, which causes neither write norerase operation even if the select transistor is in the on-state, isapplied to the other bit line B(040) and source lines S(030) and S(050).

With the above arrangement, a voltage of a potential difference of aboutVb is applied to the memory function body 604 of the memory element ofthe memory cell M(320), performing the memory operation. In the othermemory cells, since the select transistor 601 is in the off-state or thepotential difference between the bit line B and the source line S is 0 Veven if the select transistor 601 is in the on-state, no voltage isapplied to the memory function body, performing no memory operation.

FIGS. 9A and 9B show the cross-sectional structure of the memory deviceof one embodiment in which a plurality of memory cells M1, M2, M3, . . .of the type such that the aforementioned memory function body of thememory element and the select transistor are connected in series areintegrated on a silicon substrate 900. The select transistor of each ofthe memory cells M includes a drain region 903 and a source region 907,which are formed mutually apart on the surface of the silicon substrate900, a gate oxide film 908 and a gate electrode 909 that cover thesubstrate surface between the drain and source regions. The mutuallyadjacent memory cells are constructed symmetrically with respect to adirection (transverse direction in FIG. 9) parallel to the substrate900. Source regions 907 of the memory cells M1 and M2 are integrallycontinuously formed, and one source contact 902 is formed on this sourceregion 907. That is, the source contact 902 is shared by the memorycells M1 and M2. Drain regions 903 and 903 of the memory cells M2 and M3are isolated apart in the transverse direction, and one memory functionbody 904 (which has the same structure as that of the aforementionedmemory function body 113) and one bit contact 901 are formed over thosedrain regions 903 and 903. That is, the memory function body 904 isformed integrally continuously in the transverse direction so as to bein contact with the two drain regions 903 and 903. Moreover, the bitcontact 901 is shared by the memory cells M2 and M3. A corresponding bitline 926 is connected to the bit contact 901.

In this construction, the regions that perform the memory operation outof the memory function body 904 are limited to regions 905 and 905 whichare interposed between the bit contact 901 and the drain regions 903 and903 and to which a voltage is applied as shown in FIG. 9B. The memoryfunction bodies 904 are basically an insulator although it containsconductive particles. Therefore, the remaining region (corresponding tothe portion located between the regions 905 and 905) to which noeffective voltage is applied in the memory function body 904 performs nomemory operation.

Therefore, in this memory, the memory function body 904 of the memoryelement operates as a 2-bit memory function body. Therefore, theoccupation area of the memory element including the memory function body904 becomes about a half in comparison with the case where one memoryfunction body is formed on each of the drain regions 903. Moreover, thenumber of bit contacts 901 and source contacts 902 can be reduced toabout a half. Therefore, the occupation area per cell is reduced, andthe integration degree is increased.

FIGS. 10A and 10B show modification examples of the memory device shownin FIG. 9A. It is to be noted that the same components as those alreadyshown in the figures are denoted by same reference numerals, and nodescription is provided for them (applicable also hereinafter).

In these modification examples, the drain regions 903 and 903 of themutually adjacent memory cells M2 and M3 are transversely isolated apartby a trench (groove) 1003 of a sectionally rectangular shape formed onthe substrate 900. An insulation film 1001 is formed in a sectionallybracket-like shape along the substrate wall surfaces (inner walls of thetrench) that define the trench 1003, and the inside of the insulationfilm 1001 is stuffed with a conductive substance (trench electrode) 1005of, for example, polysilicon or metal. The trench electrode 1005 iselectrically connected to a bit contact 901.

In the memory device of FIG. 10A, the conductive particle, of which thesurface is covered with a second insulation film, is contained only inthe region near the substrate top surface of the insulation film 1001,constituting a memory function body 1004. In this example, the memoryfunction body 1004 reaches a depth deeper than that of the drain region903 from the substrate top surface. On the other hand, in the memorydevice of FIG. 10B, conductive particles are contained in the wholeregion of the insulation film 1001, constituting a memory function body1014.

Anyway, as shown in FIG. 10C, the regions that perform the memoryoperation in the memory function body are limited to regions 1024 and1024, which are interposed between the trench electrode 1005 and thedrain region 903 and to which a voltage is applied. The memory functionbody is basically an insulator although it contains the conductiveparticles. Therefore, the remaining region to which no effective voltageis applied in the memory function body performs no memory operation.

In these memory devices of FIGS. 10A and 10B , the occupation area ofthe memory function bodies 1004 and 1014 becomes about a half similarlyto the memory of FIG. 9 in comparison with the case where one memoryfunction body is formed on each of the drain regions 903. Moreover, thenumber of bit contacts 901 and source contacts 902 can be reduced toabout a half. Therefore, the occupation area per cell is reduced, andthe integration degree is increased.

FIG. 11 shows a memory device provided with memory cells M each of whichincludes the aforementioned memory function body and a rectifyingfunction body, the memory cells arranged in a matrix form. Word lines Wand bit lines B are extended in the direction of row and in thedirection of column, respectively. A memory element including a memoryfunction body 1204 (comprising the same configuration as theaforementioned memory function body 113) and a rectifying function body1201 of each of the memory cells M are connected in series between thecorresponding bit line B and word line W. Each rectifying function body1201 permits the flow of a current from the word line W to the bit lineB through the memory function body 1204 and obstructs the flow of acurrent from the bit line B to the word line W through the memoryfunction body 1204.

For example, in selecting the memory cell M(320), a positive voltage VHis applied to the word line W(300) connected to the memory cell, and anegative voltage VL, which provides a potential difference necessary forthe desired operation of the write, read and erase in the memoryfunction body 1204, is applied to the bit line B(020). Further, avoltage, which provides a potential difference that causes neither writenor erase in the memory function body 1204 even if the positive voltageVH is applied to the word line W, is applied to the other bit linesB(010), B(030) and B(010). For example, in order to render the potentialdifference zero, the voltage VH is applied. Likewise, the potentialdifference applied to the nonselected memory function body 1204 isrendered zero by applying the voltage VL to the other word lines W(100),W(200) and W(400).

By the above operation, a potential difference of about (VH−VL) isapplied to the memory function body 1204 of the memory cell M(320),performing the memory operation. In the other memory cells M, Thepotential difference is zero or a voltage inverted with respect to therectifying function body 1201 even if there is a potential difference.Therefore, the current is limited, and the memory function body 1204performs no memory operation.

Otherwise, it is acceptable to employ a rectifying function body 1201having a threshold value in the forward direction and permitting nocurrent or only a current that is too small to cause the memoryoperation with a potential difference smaller than Vt to flow. It is tobe noted that, if the potential difference necessary for the memoryoperation of the memory function body 1204 is assumed to be Vm, thenthere holds the expression: Vt>(Vm/2). (Vm/2). For example, in order toselect the memory cell M(320), a positive voltage (Vm/2) is applied tothe word line W(300) and a negative voltage −(Vm/2) is applied to thebit line B(020), giving a potential difference Vm necessary for thememory operation to the memory function body 1204. A voltage of 0 V isapplied to the other word lines W and bit lines B. In this case, amaximum potential difference of (Vm/2) is applied to the nonselectedmemory cells M. However, since the current is limited by the rectifyingfunction body 1201, no memory operation is performed.

FIGS. 12A through 12E show various possible structures of the memorycells that include the aforementioned memory function body and therectifying function body constructed of a pn junction.

FIG. 12A schematically shows a mode in which the memory elementincluding the memory function body 1204 (comprising the sameconfiguration as the aforementioned memory function body 113) and therectifying function body 1201 are electrically connected in series toeach other. The rectifying function body 1201 includes a pn junctionconstructed of an n-type semiconductor 1202 and a p-type semiconductor1203.

FIG. 12B schematically shows a mode in which the rectifying functionbody 1201 in FIG. 12A is formed on a semiconductor substrate (e.g.,silicon substrate) 1215. In this example, the p-type semiconductorregion 1203 and the n-type semiconductor region 1202 of the rectifyingfunction body 1201 are respectively formed through implantation,diffusion and so on of impurities into the surface of the semiconductorsubstrate 1215 by a well-known method.

FIGS. 12C through 12E concretely show the arrangements of the memoryfunction body 1204 in FIG. 12B. FIG. 12C is an example in which thememory function body 1204 is provided partway in a contact 1226. FIG.12D is an example in which the memory function body 1204 is provided incontact with the n-type semiconductor region 1202. Moreover, FIG. 12E isan example in which the memory function body 1204 is provided in contactwith a bit line 1247. The memory function body 1204 is formed by theaforementioned method, and the contacts 1226 and 1227 are formed by awell-known method.

FIGS. 13A through 13D show various structures in the case where a memoryelement and a rectifying function body constructed of a pn junction areincluded in each memory cell and the constituent elements are shared bymutually adjacent two memory cells. It is to be noted that contacts,which are expressed in a simplified style in FIGS. 13A through 13D, areformed by a well-known method.

FIG. 13A schematically shows a mode in which memory cells M11, M12, M13,. . . including the memory function bodies 1204 of the memory elementsand the rectifying function bodies 1301 are electrically connected inseries. Mutually adjacent memory cells are symmetrically constructed.Each of the rectifying function bodies 1301 includes a pn junctionconstructed of an n-type semiconductor region 1302 and a p-typesemiconductor region 1303. A word contact 1305 and a bit contact 1304are electrically connected to the p-type semiconductor region 1303 andthe memory function body 1204, respectively.

FIG. 13B shows the cross-sectional structure of a memory device in whichthe aforementioned plurality of memory cells M11, M12, M13, . . . areintegrated on a silicon substrate 1316. The n-type semiconductor regions1302 and 1302 are formed mutually apart in a direction (transversedirection in FIG. 13) parallel to the substrate 1316 in the memory cellsM11 and M12, and one memory function body 1204 and one bit contact 1304between mutually adjacent memory cells M11 and M12 are formed over thosen-type semiconductor regions 1302 and 1302. That is, the memory functionbody 1204 is formed integrally continuously in the transverse directionso as to be in contact with the two n-type semiconductor regions 1302and 1302. The p-type semiconductor region 1303 is integrallycontinuously formed between mutually adjacent memory cells M12 and M13,and one word contact 1305 is formed on the p-type semiconductor region1303. If this arrangement is adopted, the occupation area per cell isreduced, and the integration degree is increased.

In order to fabricate this memory device, an oxide film (not shown) isfirst formed on the surface of the silicon substrate 1316, and thememory function body 1204 is formed by the aforementioned method. Next,the p-type semiconductor region 1303 and the n-type semiconductor region1302 are formed through implantation, diffusion and so on of impuritiesinto the surface parts of the silicon substrate 1316. At this time, noimpurity is implanted into the region covered with the memory functionbody 1204. Subsequently, contacts 1304 and 1305 are formed by awell-known method.

FIG. 13C shows a modification example of the memory device shown in FIG.13B. In this modification example, an element isolation region 1327 isprovided between the n-type semiconductor regions 1302 and 1302 of themutually adjacent memory cells M11 and M12 by a well-known method. Ifthis arrangement is adopted, the mutually adjacent memory cells M11 andM12 can reliably be electrically isolated from each other.

FIG. 13D shows a further modification example. In this modificationexample, a trench (groove) 1333 of a sectionally rectangular shape isprovided between the n-type semiconductor regions 1302 and 1302 of themutually adjacent memory cells M11 and M12 on the substrate 1316 by awell-known method. An insulation film 1331 is formed in a sectionallybracket-like shape along the substrate wall surfaces (inner walls of thetrench) that define the trench 1333, and the inside of the insulationfilm 1331 is stuffed with a conductive substance (trench electrode) 1335of, for example, polysilicon or metal. The trench electrode 1335 iselectrically connected to the bit contact 1304. Then, conductiveparticles are contained only in the region near the substrate topsurface of the insulation film 1331, constituting a memory function body1334. In this example, the memory function body 1334 reaches a depthapproximately equal to the depth of the n-type semiconductor region 1302from the substrate top surface. If this arrangement is adopted, themutually adjacent two memory cells M11 and M12 can reliably beelectrically isolated from each other.

FIG. 14 shows a memory device provided with memory cells M each of whichincludes the memory element including the aforementioned function body,a rectifying function body and a select transistor, the memory cellsbeing arranged in a matrix form. Word lines W and bit lines B areextended in the direction of row and in the direction of column,respectively. In this example, the arrangement of the memory functionbody 1204, the rectifying function body 1201 and the select transistor1209 (which has the same structure as that of the aforementioned selecttransistor 601) is symmetrical between the memory cells M that aremutually adjacent in the direction of row. Moreover, the arrangement ofthe memory function body 1204, the rectifying function body 1201 and theselect transistor 1209 is symmetrical between the memory cells M thatare mutually adjacent via a word line W in the direction of column. Thememory function body 1204, the rectifying function body 1201 and theselect transistor 1209 of each memory cell M are connected in seriesbetween the corresponding bit line B and bit line B. It is to be notedthat each bit line B is switched over to operate also as a source line.

The memory cell M(320) is assumed as a first cell. With regard to it,memory cells M(310) and M(330), which are mutually adjacent in thedirection of row, are assumed as a second cell and a fourth cell,respectively, and the memory cells M(220) and M(420), which are mutuallyadjacent in the direction of column, are assumed as a third cell and afifth cell. The first cell M(320) and the second cell M(310) have thebit line B(020) shared, the word line W(200) shared and the source linesB(010) and B(030) unshared. The first cell M(320) and the third cellM(220) have the bit line B(020) shared, the source line B(030) sharedand the word lines W(200) and W(100) unshared. The first cell M(320) andthe fourth cell M(330) have the source line B(030) shared, the word lineW(200) shared and the bit lines B(020) and B(040) unshared. The firstcell M(320) and the fifth cell M(420) have the word line W(200) shared.The source line B(030) of the first cell M(320) and the bit line B(030)of the fifth cell M(420) are shared, and the bit line B(020) of thefirst cell M(320) and the source line B(020) of the fifth cell M(420)are shared.

For example, in selecting the first cell M(320), a voltage Vo that turnson the select transistor 1209 is applied to the word line W(200), and avoltage Vu that turns off the select transistor 1209 is applied to theother word line W(100). In addition, a high voltage VH is applied to thebit lines B(010) and B(020), and a low voltage VL is applied to theother bit lines B(030) and B(040). It is to be noted that a potentialdifference (VH−VL) is assumed to be a potential difference with which aforward current sufficient for the memory operation of the memory cell Mflows.

With the above arrangement, the potential difference and the forwardcurrent necessary for the memory operation occur are provided in thefirst cell M(320).

The cells, which are mutually adjacent in the direction of row withrespect to the first cell M(320) and sharing the bit lines B(020) andB(030) with the first cell M(320), i.e., the second cell M(310) and thefourth cell M(330) have no potential difference (no voltage is applied)regardless of whether the select transistor 1209 is turned on or off andno current flows, consequently performing no memory operation.

The cell, which is adjacent to the first cell M(320) in the direction ofcolumn and not sharing the word line W(200) but sharing both the bitlines B(020) and B(030) with the first cell M(320), i.e., the third cellM(220) has no current flow necessary for the memory operation since theselect transistor 1209 is off, consequently performing no memoryoperation.

The cell, which is adjacent to the first cell M(320) in the direction ofcolumn and sharing all of the bit lines B(020) and B(030) and the wordline W(200) with the first cell M(320), i.e., the fifth cell M(420) hasno current flow necessary for the memory operation but only a reversecurrent flows due to the rectifying function body 1201, consequentlyperforming no memory operation.

In this memory device, memory cells are able to share the bit lines andthe word lines and therefore makes it possible to reduce the number ofinterconnections and largely restrain an increase in the occupation areaattributed to the interconnections.

FIGS. 15A through 15E show various possible structures of the memorycell that includes the memory element including the aforementionedmemory function body and the rectifying function body constructed of aSchottky junction.

FIG. 15A schematically shows a mode in which a memory function body 1504(which has the same structure as that of the aforementioned memoryfunction body 113) and a rectifying function body 1501 are electricallyconnected in series. The rectifying function body 1501 includes aSchottky junction constructed of a metal 1502 and an n-typesemiconductor 1503.

FIG. 15B schematically shows a mode in which the rectifying functionbody 1501 in FIG. 15A is formed on a semiconductor substrate (e.g.,silicon substrate) 1515. In this example, the n-type semiconductorregion 1503 of the rectifying function body 1501 is formed by theimplantation, diffusion and so on of impurities into the surface part ofthe semiconductor substrate 1515 by a well-known method. A metal 1502 isformed on the region, forming a Schottky junction between the metal 1502and the n-type semiconductor 1503. A memory function body 1504 isprovided on the metal 1502 via a contact 1526. The metal 1502 and thecontact 1526 may be formed of the same material, and the number ofprocesses can be reduced because of the needlessness of differentprocesses, achieving excellent productivity.

FIGS. 15C and 15D concretely show the arrangement of the memory functionbody 1504 in FIG. 15B. FIG. 15C shows an example in which the memoryfunction body 1504 is provided partway in the contact 1526. FIG. 15Dshows an example in which the memory function body 1504 is provided incontact with the metal 1502.

In this case, in order to form the Schottky junction between the metaland the semiconductor, the impurity concentration of the semiconductor(regardless of whether n-type or p-type) should preferably have a lowconcentration of, for example, less than 10 ¹⁸/cm³. The above is becausean ohmic junction is disadvantageously formed when the impurityconcentration of the semiconductor is extremely high. Whether thesemiconductor is made to have an n-type or p-type doping depends onwhich way the rectification direction is directed. For example, if thesemiconductor is made to have an n-type doping, then the forwarddirection of the metal-to-n-type semiconductor Schottky junction is thedirection directed from the metal to the n-type semiconductor. That is,electrons move from the n-type semiconductor toward the metal.

FIG. 15E shows a mode in which the aforementioned n-type semiconductorregion 1503 is constructed of a lowly doped n-type semiconductor layer1543 put in contact with the metal 1502 and a highly doped n-typesemiconductor layer 1548 that surrounds the lowly doped n-typesemiconductor layer 1543 and is in contact with a contact 1527. Forexample, the impurity concentration of the highly doped n-typesemiconductor layer 1548 is assumed to exceed about 10 ²⁰/cm³. This isan example provided with a resistive semiconductor layer 1548. With thisarrangement, a Schottky junction can be formed between the layer 1543and the metal 1502, and an ohmic junction can be formed between thelayer 1548 and the contact 1527. Moreover, the resistance of the n-typesemiconductor region 1503 (highly doped n-type semiconductor layer 1548)can be reduced, making it possible to improve the operation speed andreduce power consumption.

In order to make an ohmic junction at the junction between the contactand the semiconductor layer, it is possible to use a method forincreasing the impurity concentration of the semiconductor layer, amethod for forming metallic silicide at the junction portion or thelike.

FIGS. 16A through 16D show various structures in the case where a memoryelement including a memory function body and a rectifying function bodyconstructed of a Schottky junction are included in each memory cell andthe constituent elements are shared by two mutually adjacent memorycells. It is to be noted that contacts, which are expressed in asimplified style in FIGS. 16A through 16D, are formed by a well-knownmethod.

FIG. 16A schematically shows a mode in which memory cells M21, M22, M23,. . . including memory function bodies 1504 and rectifying functionbodies 1601 are electrically connected in series. Mutually adjacentmemory cells are symmetrically constructed. Each of the rectifyingfunction bodies 1601 includes a Schottky junction constructed of ann-type semiconductor region 1602 and a metal layer 1603. A bit contact1605 and a word contact 1604 are electrically connected to the metallayer 1603 and the memory function body 1504, respectively.

FIG. 16B shows the cross-sectional structure of a memory device in whichthe aforementioned plurality of memory cells M21, M22, M23, . . . areintegrated on a silicon substrate 1616. The n-type semiconductor regions1602 and 1602 are formed mutually apart in a direction (transversedirection in FIG. 16) parallel to the substrate 1616 between mutuallyadjacent memory cells M21 and M22, and one memory function body 1504 andone word contact 1604 are formed over those n-type semiconductor regions1602 and 1602. That is, the memory function body 1504 is formedintegrally continuously in the transverse direction so as to be incontact with the two n-type semiconductor regions 1602 and 1602. Themetal layer 1603 is integrally continuously formed between mutuallyadjacent memory cells M22 and M23, and one bit contact 1605 is formed onthe layer1603. If this arrangement is adopted, the occupation area percell is reduced, and the degree of integration is increased.

In order to fabricate this memory device, an oxide film (not shown) isfirst formed on the surface of the silicon substrate 1616, and thememory function body 1504 is formed by the aforementioned method. Next,an n-type semiconductor region 1602 is formed by the implantation,diffusion and so on of impurities into the surface part of the siliconsubstrate 1616. At this time, no impurity is implanted into the regioncovered with the memory function body 1504. Next, a metal layer 1603 isformed so as to form a Schottky junction with the n-type semiconductorregion 1602. Subsequently, contacts 1604 and 1605 are formed by awell-known method.

FIG. 16C shows a modification example of the memory device shown in FIG.16B. In this modification example, an element isolation region 1627 isprovided between the n-type semiconductor regions 1602 and 1602 of themutually adjacent memory cells M21 and M22 by a well-known method. Ifthis arrangement is adopted, the mutually adjacent memory cells M21 andM22 can reliably be electrically isolated from each other. Moreover, then-type semiconductor region 1602 is constructed of a lowly doped n-typesemiconductor layer 1643 put in contact with the metal layer 1603 and ahighly doped n-type semiconductor layer 1648 that surrounds the lowlydoped n-type semiconductor layer 1643 and is put in contact with thememory function body 1504. With this arrangement, the resistance of then-type semiconductor region 1602 (highly doped n-type semiconductorlayer 1648) can be reduced, making it possible to improve the operationspeed and reduce power consumption.

FIG. 16D shows a further modification example. In this modificationexample, a trench (groove) 1633 of a sectionally rectangular shape isprovided between the n-type semiconductor regions 1602 and 1602 of themutually adjacent memory cells M21 and M22 on the substrate 1616 by awell-known method. An insulation film 1631 is formed into a sectionallybracket-like shape along the substrate wall surfaces (inner walls of thetrench) that define the trench 1633, and the inside of the insulationfilm 1631 is stuffed with a conductive substance (trench electrode) 1635of, for example, polysilicon or metal. The trench electrode 1635 iselectrically connected to the word contact 1604. Then, conductiveparticles are contained only in the region near the substrate topsurface of the insulation film 1631, constituting a memory function body1634. In this example, the memory function body 1634 reaches a depthapproximately equal to the depth of the n-type semiconductor region 1602from the substrate top surface. If this arrangement is adopted, themutually adjacent two memory cells M21 and M22 can reliably beelectrically isolated from each other. Moreover, similarly to FIG. 16C,the n-type semiconductor region 1602 is constructed of a lowly dopedn-type semiconductor layer 1643 put in contact with the metal layer 1603and the highly doped n-type semiconductor layer 1648 that surrounds thelowly doped n-type semiconductor layer 1643 and is put in contact withthe memory function body 1634. With this arrangement, the resistance ofthe n-type semiconductor region 1602 (highly doped n-type semiconductorlayer 1648) can be reduced, making it possible to improve the operationspeed and reduce power consumption.

FIG. 17A is a view showing the three-dimensional spatial structure of amemory device in which a plurality of aforementioned memory functionbodies 1710 and 1720 are arranged in a direction perpendicular to asubstrate; FIG. 17B is a view showing electrical connection of theconstituent elements in FIG. 17A. Interlayer insulation film is notdepicted in FIG. 17A.

This memory device is provided with a plurality of interconnections1701, 1702, 1703, . . . extended parallel to the substrate (not shown)at mutually different heights. A lower layer interconnection 1701 and anupper layer interconnection 1703 are parallel to each other, while anintermediate layer interconnection 1702 intersect theseinterconnections. A memory function body 1710 (which has the samestructure as that of the aforementioned memory function body 113) isprovided so as to be interposed between those interconnections 1701 and1702 via a contact 1706 in a portion in which the interconnection 1701and the interconnection 1702 intersect each other. With thisarrangement, a memory cell is constructed in the portion in which themetal interconnection 1701 and the metal interconnection 1702 intersecteach other. Likewise, a memory function body 1720 (which has the samestructure as that of the aforementioned memory function body 113) isprovided so as to be interposed between those interconnections 1702 and1703 via a contact 1716 in a portion in which the interconnection 1702and the interconnection 1703 intersect each other, constituting a memorycell. In other words, the memory function bodies 1710 and 1720 areprovided so as to interpose or substitute the contacts 1706 and 1716.

In this structure of FIG. 17A, the memory function bodies 1710 and 1720are three-dimensionally integrated, and therefore, it is possible tolargely reduce the effective occupation area and increase the memorycapacity.

FIG. 18A shows a memory device, which has a three-dimensional spatialstructure of the aforementioned type and in which each memory cellincludes a memory element including a memory function body and arectifying .function body. FIG. 18C shows the electrical connection ofthe constituent elements in FIG. 18A.

This memory device is provided with a plurality of metalinterconnections 1801, 1802, 1803A, . . . extended at different heightsfrom a top surface of a substrate (not shown). The lower layer metalinterconnection 1801 and the upper layer metal interconnection 1803A areparallel to each other, and an intermediate layer metal interconnection1802 intersects these interconnections 1801 and 1803A. A semiconductor1820 is provided in a portion in which the metal interconnection 1801and the metal interconnection 1802 intersect each other so as to form aSchottky junction in contact with the metal interconnection 1801. Themetal interconnection 1801 and the semiconductor 1820 constitute arectifying function body. A memory function body 1810 (which has thesame structure as that of the aforementioned memory function body 113)is provided so as to be interposed between the semiconductor 1820 andthe metal interconnection 1802 that constitute the rectifying functionbody (the semiconductor 1820 and the metal interconnection 1802 areelectrically isolated from each other by the memory function body 1810).With this arrangement, a memory cell is constructed in a portion inwhich the metal interconnection 1801 and the metal interconnection 1802intersect each other. Likewise, the semiconductor 1820 and the memoryfunction body 1810 are provided in quite the same style in a portion inwhich the metal interconnection 1802 and the metal interconnection 1803Aintersect each other, constituting a memory cell 1832A. Further, thesemiconductor 1820 and the memory function body 1810 are provided inquite the same style in a portion in which the metal interconnection1803A and a metal interconnection of its upper layer (not shown)intersect each other, constituting a memory cell 1833A.

FIG. 18B show a modification example of the memory device shown in FIG.18A. In the structure of FIG. 18A, for example, the memory cells 1833Aand 1832A arranged above and below the metal interconnection 1803A arearranged in a line in the vertical direction. In contrast to this, inthe structure of this FIG. 18B, an upper layer metal interconnection1803B is arranged displaced in the transverse direction (directionperpendicular to the lengthwise direction of this interconnection 1803B)with respect to the lower layer metal interconnection 1801. In addition,for example, a memory cell 1833B arranged upward with respect to thememory cell 1832B arranged below the metal interconnection 1803B, isarranged displaced in the lengthwise direction of this interconnection1803B. As a result, in this structure of FIG. 18B, a spatial averagedistance between memory cells is greater than that of the structure ofFIG. 18A. Therefore, mutual influence on the memory cells becomes lessexerted, and the reliability of the memory is improved.

Next, a method for fabricating a memory device that has athree-dimensional spatial structure of the type shown in FIG. 18A willbe described with reference to FIGS. 19A through 19J. FIGS. 19A, 19B,19C, 19D and 19E show the states of an object in fabrication stagesviewed from the same direction. FIGS. 19F, 19G, 19H, 19I and 19J showthe states of the object of FIGS. 19A, 19B, 19C, 19D and 19E viewed fromthe right-hand side, respectively.

First of all, as shown in FIGS. 19A and 19F, a metal interconnectionlayer 1901, a semiconductor layer (e.g., polysilicon layer) 1902 forforming a Schottky junction with this metal interconnection layer and amemory function body layer 1903 are successively laminated in the wholearea on a substrate (not shown). The memory function body layer 1903 isformed by forming, for example, a silicon oxide film and thereafterimplanting ions of conductive particles in the silicon oxide film so asto provide the same structure as that of the aforementioned memoryfunction body 113.

Next, as shown in FIGS. 19B and 19G, the layers 1903, 1902 and 1901 arecollectively etched and processed into a linear pattern extended in onedirection. If the etching is collectively effected as described above,then the process can be simplified than when the etching is repeated foreach of the layers 1903, 1902 and 1901. It is to be noted that aninterlayer insulation film (not shown) of, for example, silicon oxide isdeposited in the whole area after this etching, and the surface isflattened by a CMP (Chemical-Mechanical Polishing) method.

Next, as shown in FIGS. 19C and 19H, a metal interconnection layer 1924,a semiconductor layer 1925 for forming a Schottky junction with thismetal interconnection layer and a memory function body layer 1926 aresuccessively repetitively laminated in the whole area on this film.

Next, as shown in FIGS. 19D and 19I, the layers 1924, 1925 and 1926 arecollectively etched to carry out pattern processing in a linear formextended crosswise roughly perpendicularly to the direction in which thelayers 1903, 1902 and 1901 are extended. If the etching is collectivelyeffected as described above, then the process can be simplified thanwhen the etching is repeated for each of the layers 1924, 1925 and 1926.In this stage, a first layer memory cell, which includes thesemiconductor layer 1902 and the memory function body 1903 that haveundergone the pattern processing, is formed in a portion in which thelower layer metal interconnection 1901 and the metal interconnection1924 on it intersect each other. After this etching, an interlayerinsulation film (not shown) of, for example, silicon oxide is depositedagain in the whole area, and the surface is flattened by the CMP method.

Subsequently, as shown in FIGS. 19E and 19J, the deposition andcollective etching of a metal layer 1947 to be a metal interconnection,a semiconductor layer 1948 and a memory function body layer 1949 arerepeated in a similar manner. In this stage, a second layer memory cell,which includes the semiconductor layer 1925 and the memory function body1926 that have undergone the pattern processing, is formed in a portionin which the metal interconnection 1924 and the metal interconnection1947 on it intersect each other.

By thus repeating the deposition and collective etching of the metallayer, the semiconductor layer and the memory function body layer, amemory device that has a three-dimensional spatial structure can befabricated.

It is to be noted that a third layer memory cell, which includes thesemiconductor layer 1948 and the memory function body layer 1949 thathave undergone the pattern processing, is formed by the next collectiveetching.

As already described hereinabove, the memory function body is basicallyan insulator although it contains conductive particles. Therefore, theremaining portion to which no effective voltage is applied in the memoryfunction body performs no memory operation.

For example, as shown in FIG. 20A, it is assumed that a pair of upperand lower electrodes 2003, 2002; 2003, 2002; . . . arranged withinterposition of a memory function body layer 2001 are arranged mutuallyapart in the layer direction (transverse direction in FIG. 20A). In thiscase, if a voltage is applied to, for example, the pair of electrode2003 and 2002 located at the right-hand end, the region that performsthe memory operation in the memory function body layer 2001 is limitedto the neighborhood of a region 2004A between the pair of electrodes2003 and 2002 located at the right-hand end. Therefore, a region 2004Bbetween the pair of the central electrodes 2003 and 2002 to which novoltage is applied causes no malfunction.

Moreover, as shown in FIG. 20B, it is assumed that an interconnectionlayer 2012 is formed extended in the transverse direction under a memoryfunction body layer 2011, and interconnection layers 2013, 2013, . . .extended in the depthwise direction (direction perpendicular to thesheet plane of FIG. 20) are arranged mutually apart on the memoryfunction body layer 2011. Also, in this case, when a voltage is appliedacross, for example, the interconnection layer 2012 and theinterconnection layer 2013 located at the right-hand end, the regionthat performs the memory operation in the memory function body layer2011 is limited to the neighborhood of a region 2014A in which thoseinterconnection layers 2012 and 2013 intersect each other. Therefore, aregion 2014B interposed between the interconnection layer 2012 and thecentral interconnection layer 2013 causes no malfunction.

As described above, the remaining portion to which no effective voltageis applied in the memory function body layer performs no memoryoperation. Therefore, it is possible to put the memory function bodylayer into an integrated continuous state without being divided intomemory cells. If the above arrangement is adopted, it is possible toprevent damage due to etching from being given to the region thatperforms the memory operation and improve the reliability of the memory.

A method for fabricating the memory function body layer integrallycontinuously in the layer direction in fabricating a memory that has athree-dimensional spatial structure will be described next. FIGS. 21A,21B, 21C, 21D and 21E show the states of an object in fabrication stagesviewed from the same direction. FIGS. 21F, 21G, 21H, 21I and 21J showthe states of the object of FIGS. 21A, 21B, 21C, 21D and 21E viewed fromthe right-hand side, respectively.

First of all, as shown in FIGS. 21A and 21F, a metal interconnectionlayer 2101 and a semiconductor layer (e.g., polysilicon layer) 2102 forforming a Schottky junction with the metal interconnection layer 2101are successively laminated in the whole area on a substrate (not shown).These layers 2102 and 2101 are collectively etched and patterned into alinear form extended in one direction. Further, the semiconductor layer2102 is etched and separated every memory cell. After this etching, aninsulator layer 2103, which should become an interlayer insulation filmof, for example, silicon oxide, is deposited to a sufficient thicknessin the whole area, and the surface is flattened by the CMP method asshown in FIGS. 21B and 21G. This flattening is effected not until theupper surface of the semiconductor layer 2102 is exposed but until thethickness of the insulator layer 2103 on the semiconductor layer 2102becomes equivalent to the thickness of the memory function body layer tobe formed in the next process.

Next, as shown in FIGS. 21C and 21H, ions of conductive particles areimplanted in the region above the upper surface of the semiconductorlayer 2102 in the insulator layer 2103, forming a memory function bodylayer 2104. The memory function body layer 2104 has the same structureas that of the aforementioned memory function body 113 and is formedinto a state in which it is put in contact with the semiconductor layer2102 and extended integrally continuously in the layer direction in thewhole area on the substrate.

Next, as shown in FIGS. 21D and 21I, a metal interconnection layer 2105and a semiconductor layer 2106 for forming a Schottky junction with thismetal interconnection layer are successively laminated again in thewhole area. These layers 2106 and 2105 are collectively etched andpatterned into a liner form extended crosswise roughly perpendicularlyto the direction in which the metal layer 2101 is extended. Further, thesemiconductor layer 2106 is etched and separated every memory cell.After this etching, an insulator layer 2107, which should become aninterlayer insulation film of, for example, silicon oxide, is depositedto a sufficient thickness in the whole area, and the surface isflattened by the CMP method as shown in FIGS. 21E and 21J. Thisflattening is effected not until the upper surface of the semiconductorlayer 2106 is exposed but until the thickness of the insulator layer2107 on the semiconductor layer 2106 becomes equivalent to the thicknessof the memory function body layer to be formed in the next process.

Subsequently, by repeating similar processes, a three-dimension spatialstructure as shown in FIGS. 21E and 21J is obtained. FIGS. 21E and 21Jshow a state in which the three sets of the metal interconnection layer,the semiconductor layer and the memory function body layer arelaminated. In the figures, there are shown a memory function body layer2108, a metal interconnection layer 2109, a semiconductor layer 2110, aninterlayer insulation film (insulator layer) 2111 and a memory functionbody layer 2112.

In this structure, as is apparent from FIG. 21E, the memory cell 2134,which is arranged on the metal interconnection 2109, is displaced in thelengthwise direction of the interconnection 2109 with respect to, forexample, the memory cell 2124 arranged below the metal interconnection2109. Moreover, as is apparent from FIG. 21J, the memory cell 2124,which is arranged on the metal interconnection 2105, is displaced in thelengthwise direction of the interconnection 2105 with respect to, forexample, the memory cell 2114 arranged below the metal interconnection2105. As a result, in this structure, a spatial average distance betweenthe memory cells is made greater than in the case where the memory cellsare arranged in a line in the vertical direction. Therefore, mutualinfluence on the memory cells becomes less exerted, and the reliabilityof the memory device is improved.

FIGS. 22A and 22B show a modification example of the structure shown inFIGS. 21E and 21J. FIG. 22B shows a state in which the object of FIG.22A is viewed from the right-hand side.

In this modification example, contact 2205 is provided between thememory function body layer 2104 and both the metal interconnection layer2105 and the semiconductor layer 2102, that is, the contact 2205 islocated above and below the memory function body layer 2104. In the sameway, contact 2205 is provided between the memory function body layer2108 and both the metal interconnection layer 2109 and the semiconductorlayer 2106. In the same way, contact 2205 is provided between the memoryfunction body layer 2112 and both the metal interconnection layer 2113and the semiconductor layer 2110.

It is a matter of course that a structure in which the memory functionbody layer is separated into memory cells can be employed in FIGS. 21E,21J, 22A and 22B.

FIGS. 23A and 23B show another modification example of the structureshown in FIGS. 21E and 21J. FIG. 23B shows a state in which the objectof FIG. 23A is viewed from the right-hand side.

In this modification example, a rectifying function body constructed ofa pn junction is provided in place of the rectifying function bodyconstructed of the Schottky junction. That is, a pair of p-typesemiconductor layer 2353 and an n-type semiconductor layer 2352, whichconstitute a pn junction, is provided between the metal interconnectionlayer 2101 and the memory function body layer 2104. In the same way, apair of p-type semiconductor layer 2353 and an n-type semiconductorlayer 2352 is provided between the metal interconnection layer 2105 andthe memory function body layer 2108. In the same way, a pair of p-typesemiconductor layer 2353 and an n-type semiconductor layer 2352 isprovided between the metal interconnection layer 2109 and the memoryfunction body layer 2112.

It is acceptable to interchange the positions of the p-typesemiconductor layer and the n-type semiconductor layer. By interchangingthe positions of the p-type with the n-type, the direction ofrectification can be reversed.

The structure of FIGS. 23A and 23B can be fabricated through processessimilar to those of the example of FIGS. 22A and 22B except for theprocess for constructing two layers of the p-type semiconductor layerand the n-type semiconductor layer.

In general, the barrier height of the pn junction diode can be adjustedby changing impurity concentration more easily than that of the Schottkyjunction diode. Therefore, when the rectifying function body constructedof the pn junction is employed in place of the rectifying function bodyconstructed of the Schottky junction, the characteristics of therectifying function body can easily be adjusted and excellent ingenerality. For example, if the barrier height is adjusted, then theamount of current that flows at a constant voltage or the capacitancecan be changed, and the memory operation voltage can easily be adjusted.

FIGS. 24A and 24B show a modification example of the structure shown inFIGS. 23A and 23B. FIG. 24B shows a state in which the object of FIG.24A is viewed from the right-hand side.

In this modification example, a semiconductor layer 2451, which is putin contact with a metal interconnection layer out of the twosemiconductor layers that constitute a pn junction as a rectifyingfunction body, is extended in a linear form along the metalinterconnection layer. That is, the semiconductor layers 2451, 2451 and2451, which are put in contact with the metal interconnection layers2101, 2105 and 2109, respectively, are not separated every memory cellbut processed into the same patterns as those of the metalinterconnection layers 2101, 2105 and 2109, respectively.

Since the semiconductor layer has a resistance higher than that ofmetal, it is more preferable that the semiconductor layer is extended ina linear form along, for example, the metal interconnection layer thatconstitutes the bit line like the structure of FIGS. 24A and 24B thanwhen separated every memory cell. With this arrangement, it is possibleto effectively reduce the resistance by making the semiconductor layer2451 shared by at least two memory cells.

In detail, the semiconductor layer 2353 is separated every memory cellin the structure shown in FIGS. 23A and 23B. Therefore, the position ofthe path of the current flowing from the metal interconnection 2101 tothe memory function body 2104 is limited to the inside of the pattern ofeach individual semiconductor layer 2353 as indicated by arrow in FIG.25A. In contrast to this, in the structure shown in FIGS. 24A and 24B,the position of the path of the current flowing from the metalinterconnection 2101 to the memory function body 2104 expands in adirection along the metal interconnection 2101 as indicated by arrow inFIG. 25B. Therefore, the effective cross-section area of theinterconnection increases to reduce the resistance. This consequentlyenables the high-speed operation of the memory.

It is a matter of course that the effect of the semiconductor layer 2451extended in a linear form along the metal interconnection layer is takennot only in the case where the memory function body 2504 is extendedintegrally continuously in the layer direction but also in the casewhere the memory function body 2504 is separated every memory cell.

FIGS. 26A and 26B show examples of the memory elements in which a thirdelectrode 2603 is adjacent to the memory function body 113 providedbetween the first electrode 2601 and the second electrode 2602 from adirection H1 (this is called the “layer direction”) perpendicular todirections V1 and V2 in which the first electrode 2601 and the secondelectrode 2602 are opposed to each other. That is, the third electrode2603 can apply a voltage to the memory function body 113 in a positionbetween the first electrode 2601 and the second electrode 2602 in thedirection in which the first electrode 2601 and the second electrode2602 are opposed to each other. The memory function body 113 (siliconoxide film 101) is interposed between the first electrode 2601 and thesecond electrode 2602 in the thickness directions V1 and V2. In contrastto this, in the example of FIG. 26B, the electrode arrangement withrespect to the memory function body 113 is different, so that the memoryfunction body 113 is interposed between a first electrode 2611 and asecond electrode 2612 in the layer directions H1 and H2, and a thirdelectrode 2613 is adjacent to the memory function body 113 in thethickness direction V1.

In the memory element of FIG. 26A, by grounding the second electrode2602 and applying a voltage to the first electrode 2601, there wasobserved a current that flowed between those electrodes 2601 and 2602.Moreover, in the memory element of FIG. 26B, by grounding the secondelectrode 2612 and applying a voltage to the first electrode 2611, therewas observed a current that flowed between those electrodes 2611 and2612. In either of the above cases, the observation was carried out whenthe third electrode 2603 was grounded and when a voltage was applied tothe third electrode 2603 and 2613.

Under the condition that the third electrodes 2603 and 2613 weregrounded, there was observed a difference in the current-to-voltage(I–V) characteristic between the memory element of FIG. 26A and thememory element of FIG. 26B, whereas a hysteresis characteristic appearedin either of the above cases. Under the condition that the voltage wasapplied to the third electrodes 2603 and 2613, it was discovered thatthe width of the memory window (hysteresis) increased in either of theabove cases in comparison with the case where the third electrodes 2603and 2613 were grounded. This means that the memory function is improvedwhen the voltage is applied to the third electrodes 2603 and 2613. Withthis arrangement, read errors in reading the storage state are reduced,and the reliability of the memory element is improved.

FIGS. 27A through 27E show a method for fabricating a memory elementthat has an electrode arrangement of the type shown in FIG. 26B on thesurface of a semiconductor substrate.

First of all, as shown in FIG. 27A, a silicon nitride film 2701 isdeposited as a mask for oxidation on a semiconductor substrate of, forexample, a silicon substrate 2700, and an opening 2701 a is formed in aprescribed region of this silicon nitride film. Then, as shown in FIG.27B, a silicon oxide film 2712 as an insulator is formed in asuperficial region (region in which the memory function body should beformed) of the silicon substrate 2700 by oxidizing the silicon substrate2700 from its surface through the opening 2701 a similarly to theordinary element isolation process.

Next, as shown in FIG. 27C, ion implantation of a semiconductor or ametal is effected in the silicon oxide film 2712, forming conductiveparticles 2723 in the silicon oxide film 2712. In this example, silverwas introduced into the silicon oxide film 2712 by the negative ionimplantation method similarly to the aforementioned method. In thisexample, heat treatment was further carried out. This heat treatment,which can also be eliminated, should preferably be carried out. This isbecause the particle diameter and the distribution of the conductiveparticles 2723 can be adjusted, and the recovery of implantation defectsand so on can be achieved if heat treatment is carried out. As describedabove, a memory function body 2715, which has the same structure as thatof the aforementioned memory function body 113, is formed.

Next, as shown in FIG. 27D, a gate electrode 2734 is formed as a thirdelectrode on the memory function body 2715 by a method similar to thatof the formation of the gate electrode of the well-known MOS transistor.In this case, it is preferable to form the gate electrode 2734 with thesilicon nitride film 2701 left. This is because the manufacturingvariation is consequently reduced since the positional relation betweenthe gate electrode 2734 and the memory function body 2715 is determinedin a self-aligning manner.

After removing the silicon nitride film 2701, a source region 2745 and adrain region 2746 as first and second electrodes are formed so as toplace the memory function body 2715 therebetween from both sides in thelayer direction (transverse direction in FIG. 27E) by implantingimpurity ions into the surface of the semiconductor substrate 2700 withthe gate electrode 2734 served as a mask as shown in FIG. 27E.

The memory element, which has the electrode arrangement of the typeshown in FIG. 26B, can be thus fabricated on the surface of thesemiconductor substrate 2700. In the fabricated memory element, themagnitude of the current that flows through the memory function body2715 is changed before and after a prescribed voltage is applied acrossthe source region 2745 and the drain region 2746, and the storage state(written state or erased state) is discriminated according to themagnitude of the current.

FIGS. 28A through 15E show another method for fabricating a memoryelement that has the electrode arrangement of the type shown in FIG. 26Bon the surface of a semiconductor substrate.

First of all, as shown in FIG. 28A, a silicon oxide film 2802 is formedon a silicon substrate 2800 by thermal oxidation. Subsequently,similarly to the aforementioned method, silver ions are introduced intothe silicon oxide film 2802 by the negative ion implantation method,forming a memory function body 2815 in a layer form including conductiveparticles 2823 in the silicon oxide film 2802. Subsequently, a substancefor forming a third electrode of, for example, polysilicon 2804 isdeposited in the whole area on the memory function body 2815.

Next, as shown in FIG. 28B, a gate electrode 2804 (denoted by the samereference numerals as those of the aforementioned polysilicon for thesake of easy understanding) as a third electrode is formed on the memoryfunction body 2815 by a method similar to that of the pattern formationof the gate electrode of the well-known MOS transistor.

Next, as shown in FIG. 28C, oxidation is carried out to form a siliconoxide film 2826 on the surface of the silicon substrate 2800, and asilicon oxide film 2827 is formed on the surface of the gate electrode2804.

Next, as shown in FIG. 28D, polysilicon sidewalls 2836 and 2837 as thefirst and second electrodes are formed so as to place the memoryfunction body 2815 therebetween from both sides in the layer direction(transverse direction in FIG. 28E) by using a well-known method. Thepolysilicon sidewalls 2836 and 2837 are electrically insulated withrespect to the silicon substrate 2800 and the gate electrode 2804 by thesilicon oxide films 2826 and 2827.

Next, after an interlayer insulation film (not shown) is formed on this,the well-known contact process is carried out as shown in FIG. 28E,forming contact interconnections 2848, 2849 and 2850 on the polysiliconsidewalls 2836 and 2837 and the gate electrode 2804, respectively.

It is desirable to distribute the conductive particles 2823 on the sidenear the silicon substrate 2800 with regard to the thickness directionof the silicon oxide film 2802 inside the memory function body 2815 (seeFIG. 28A). The reason for the above is to form the conductive particles2823 so that the particles are apart from the third electrode (gateelectrode) 2804, thereby preventing useless memory operation from beingperformed between the first and second electrodes (polysiliconsidewalls) 2836 and 2837 and the third electrode (gate electrode) 2804.In concrete, there can be used a method for carrying out ionimplantation for forming the conductive particles so that theimplantation depth becomes sufficiently deeper than the top surface ofthe silicon oxide film, a method for forming an insulator film betweenthe memory function body 2815 and the gate electrode 2804 and so on.

FIGS. 29A and 29B show the structure of a memory device in which aplurality of the aforementioned memory elements are arranged in thedirection perpendicular to the substrate and three-dimensionallyintegrated. FIG. 29A shows a plan layout when the memory device isviewed from the upper side with the interlayer insulation film removed,while FIG. 29B shows a cross section taken along the line and shown byarrows B–B′ in FIG. 29A. In the figures, there are shown a memoryfunction body 2904, a first electrode 2902, a second electrode 2903 anda third electrode 2905. The contact interconnection 2907 electricallyconnects a plurality of second electrodes 2903, 2903, . . . arranged inthe direction perpendicular to the substrate.

Since this memory device is three-dimensionally integrated, it ispossible to largely reduce the effective occupation area and increasethe memory capacity.

Although not shown in figures, the substrate can be provided by, forexample, a glass substrate, a silicon substrate whose upper layer isoxidized or the like. The conventional floating gate type memory, basedon the normal MOS transistor, is therefore generally fabricated on asilicon substrate. However, the memory device of the present inventionis not necessarily be fabricated on a silicon substrate.

A method for fabricating a memory device that has a three-dimensionalspatial structure of the type shown in FIGS. 29A and 29B will bedescribed next by using FIGS. 30 and 31.

FIGS. 30A through 30E show the sectional views of the memory device inthe processing stages.

First of all, as shown in FIG. 30A, an insulator film 3001 of a siliconoxide film or the like and a silicon film 3002 are successivelylaminated on a groundwork or a substrate 3000. Subsequently, a siliconnitride film 3003 is deposited as a mask for oxidation on the siliconfilm 3002, and openings 3003 a are formed in prescribed regions of thissilicon nitride film. Then, as shown in FIG. 30B, the silicon film 3002is oxidized from its surface through the openings 3003 a, forming asilicon oxide film 3018 as an insulator in the prescribed regions(regions in which memory function bodies should be formed) of thesilicon film 3002.

Subsequently, silver is introduced into the silicon oxide film 3018 bythe negative ion implantation method by using a mask (not shown)similarly to the aforementioned method, and heat treatment is furthercarried out, forming a memory function body 2904. It is to be noted thatthe region left unoxidized in the silicon film 3002 is used as a firstelectrode 2902 and a second electrode 2903.

Next, as shown in FIG. 30C, a material for forming a third electrode of,for example, polysilicon is deposited in the whole area on this, forminga gate electrode 2905 as the third electrode on the memory function body2904 by a method similar to that of the pattern formation of the gateelectrode of the well-known MOS transistor. Subsequently, an interlayerinsulation film 3026 is formed in the whole area on this. Then, thesurface of this interlayer insulation film 3026 is flattened by the CMP(Chemical-Mechanical Polishing) method or the like.

Subsequently, a silicon film 3032 is laminated again in the whole areaon the interlayer insulation film 3026. Then, by repeating the processessimilar to the aforementioned processes, a second layer memory functionbody 2904, a first electrode 2902, a second electrode 2903 and a thirdelectrode 2905 are formed as shown in FIG. 30D. Subsequently, aninterlayer insulation film 3056 is formed in the whole area on this.Then, the surface of this interlayer insulation film 3056 is flattenedby CMP or the like.

The layers are thus increased to the desired number of layers, andthereafter, a contact interconnection 2907 is formed so as to connectthe second electrodes 2903, 2903, . . . in the direction perpendicularto the substrate 3000.

FIGS. 31A through 31F show plan layouts when the memory device in thefabrication processes is viewed from the upper side.

As shown in FIG. 31A, the silicon film 3002 is formed in the whole areaon the substrate.

Next, as shown in FIG. 31B, the silicon film 3002 is partially oxidizedleaving the portions that become the first electrodes 2902 and thesecond electrodes 2903, forming a silicon oxide film 3018. The firstelectrodes 2902 are each extended in a linear form in the verticaldirection in FIG. 31B. On the other hand, the second electrodes 2903have a rectangular pattern and are individually isolated in the siliconoxide film 3018. The silicon oxide film 3018 also plays the role ofelement isolation. A plurality of second electrodes 2903 are arrangedalong the vertical direction at the center of the distance betweenmutually adjacent first electrodes 2902 and 2902.

Next, as shown in FIG. 31C, a memory function body 2904 is formed ineach rectangular region interposed between the first electrode 2902 andthe second electrode 2903 inside the silicon oxide film 3018. Asectional view at this time corresponds to FIG. 30B.

Next, as shown in FIG. 31D, a gate electrode 2905 as the third electrodeis formed in a linear form extended in the vertical direction so as toextend over a plurality of memory function bodies 2904 arranged parallelin the vertical direction.

Next, as shown in FIG. 31E, an interlayer insulation film 3026 is formedin the whole area on this. A sectional view at this time corresponds toFIGS. 30C and 30D.

Subsequently, as shown in FIG. 31F, a contact interconnection 2907 isformed in a position in which the contact interconnection 2907penetrates the second electrode 2903. A sectional view at this timecorresponds to FIG. 30E.

Moreover, although the first electrode 2902 and the third electrode 2905are extended as interconnections parallel in the vertical direction inthis example, the present invention is not limited to this. Ifmulti-layer interconnections are provided similarly to the fabricationof ordinary integrated circuits, then the interconnection for the firstelectrode 2902, the interconnection 2907 for the second electrode 2903and the interconnection for the third electrode 2905 can be formed so asto intersect one another.

For example, FIG. 32A shows the structure of a memory device in whichthe interconnections connected to the first, second and third electrodesare substantially perpendicular to one another. FIGS. 32B, 32C and 32Dshow the memory device of FIG. 32A viewed from the direction B, thedirection C and the direction D, respectively.

In this memory device, the first electrode 3209, the second electrode3202 and the third electrode 3205 are put in contact with the memoryfunction body 3204 from the left-hand side, from the right-hand side andfrom the upper side, respectively, in FIG. 32A. A first interconnection3229 extended forwardly depthwise in FIG. 32A is electrically connectedto the first electrode 3209 via a contact 3219. A second interconnection3207 extended in the vertical direction in FIG. 32A is electricallyconnected to the second electrode 3202. A third interconnection 3225extended in the transverse direction in FIG. 32A is electricallyconnected to the third electrode 3205 via a contact 3215.

As described above, if the interconnections connected to the first,second and third electrodes are arranged substantially perpendicularlyto one another, it is possible to further largely reduce the occupationarea of the memory device and increase the memory capacity.

FIG. 33A shows a schematic plan layout of a semiconductor device 4600according to one embodiment.

This semiconductor device 4600 is provided with a memory circuit 4601that has the aforementioned memory elements (memory cells), a peripheralcircuit 4602 that has a logic circuit and a function circuit 4603 thathas a function other than those of the memory circuit and the peripheralcircuit in a state in which the components are integrated on anidentical semiconductor substrate.

FIG. 33B shows a schematic plan layout of a conventional semiconductordevice 4610 for the sake of comparison. The memory circuit 4611 isintegrated with a flash memory that has a conventional floating gate.This conventional semiconductor device 4610 needs a booster circuit anda control circuit for the peripheral circuit 4612 since the drivingvoltage of the flash memory is higher than the driving voltage of thelogic circuit. Moreover, it is required to increase the gate oxide filmthickness of the transistor of the peripheral circuit to endure a highdriving voltage of the memory circuit, and therefore, the occupationarea of the peripheral circuit 4612 has conventionally been enlarged.Therefore, it has been difficult to miniaturize the semiconductordevice. Moreover, since the occupation areas of the memory circuit 4611and the peripheral circuit 4612 have been large, the occupation arearatio of the function circuit 4613 for another function has been limitedto a small value.

In contrast to this, the memory circuit 4601 that has the memory elementof the present invention can operate with a low voltage, and therefore,this semiconductor device 4600 can operate with the same power voltageas that of the peripheral circuit 4602. Therefore, it is possible toshare the power source by the memory circuit 4601 and the peripheralcircuit 4602 and remove the conventional booster circuit and the controlcircuit. As a result, the occupation area of the peripheral circuit 4602can be reduced. Moreover, since the driving voltage of the memorycircuit 4601 is low, the gate oxide film of the transistor included inthe peripheral circuit 4602 can be reduced in thickness, and theoccupation area of the peripheral circuit 4602 can be reduced.Furthermore, since the memory circuit 4601 can be highly integrated, theoccupation area of the memory circuit 4601 can be reduced. With thesefactors, this semiconductor device 4601 can consequently be made smallerthan the conventional semiconductor device 4610. Moreover, since theoccupation area of the function circuit 4603 other than the memorycircuit and the peripheral circuit can be expanded, a semiconductordevice of a performance higher than that of the conventional one can beconstructed.

Otherwise, if the same occupation area as that of the conventionalsemiconductor device 4610 is permitted for this semiconductor device4600, it is possible to increase the storage capacity of thesemiconductor device by integrating more memory elements than in theconventional case. With this arrangement, it becomes possible totemporarily read a large-scale program, retain the program even afterthe power is turned off and execute the program after the power isturned on again, and it also becomes possible to replace the programwith another program.

FIG. 34 schematically shows the construction of a portable telephone4700 provided with the aforementioned semiconductor device as oneexample of the electronic equipment of the present invention.

In this portable telephone 4700, a main body 4710 is equipped with anantenna section 4715, an RF circuit section 4713, a display section4714, a control circuit 4711 as a semiconductor device and a battery4712 for supplying electric power to these constituent elements. Thereference numerals 4716 and 4717 denote a signal line and a power line,respectively.

The control circuit 4711 is an LSI (Large Scale Integrated circuit) inwhich a memory circuit having the memory elements of the presentinvention and a logic circuit are consolidated and controls the RFcircuit section 4713 and the display section 4714. The control circuit4711 has the semiconductor device of the present invention built-in.Therefore, this portable telephone is able to have high functions andreduced power consumption, allowing the battery life to be remarkablyprotracted.

Although the portable telephone was constructed as one example of theelectronic equipment in the present embodiment, similar effects can betaken even if another electronic equipment such as a portableinformation terminal or a game machine is constructed.

Although the silicon oxide was employed as the material of the insulator101 that is the first insulator in the aforementioned embodiments, it isacceptable to employ silicon nitride, aluminum oxide, titanium oxide,zirconium oxide, hafnium oxide and so on. Furthermore, when the particlesurface is covered with an insulator as in the one embodiment of thepresent invention, the insulator 101 is not required to be formed of aninsulative substance.

Moreover, although silver was employed as the material that constitutesthe conductive particles, it is also acceptable to employ another metalsuch as copper, aluminum, tin, nickel, zinc, hafnium, zirconium,manganese, tantalum, titanium, tungsten, indium or gallium as a materialfor constituting the particles 103. Moreover, it is also possible toemploy a semiconductor or a compound semiconductor of silicon, germaniumor the like or employ an alloy or another compound. Moreover, even amagnetic material can be employed. However, a single element ispreferable since the implantation thereof is easy. Moreover, theinsulator that covers the particle surface may be anything so long asthe insulator has a good insulative property among the compounds of theoxides and nitrides of the substance that constitutes the particles.

Moreover, although the silicon substrate has been employed as the secondelectrode 112, it is acceptable to employ a substrate constructed of asemiconductor other than silicon or a metal material. Moreover, it isacceptable to form a conductive layer on a substrate constructed of aninsulator material such as a glass substrate by the CVD (Chemical VaporDeposition) method, the deposition, the MBE (Molecular Beam Epitaxy)method or the like and use the conductive layer as the second electrode.

The semiconductor layer, which constitutes the rectifying function body,can be formed through epitaxial growth and polysilicon deposition, andCGS (Continuous Grain Silicon) or the like can be employed. However, itis preferable to employ polysilicon or CGS, which can be formed at acomparatively low temperature. It is more preferable to employ CGS ofgood crystallinity in terms of improving the rectification capabilityand excellence in reliability. The CGS is a silicon that can befabricated at a low temperature by the fabrication method described inJapanese Unexamined Patent Application No. H8-78329 and so on and hasthe advantages that it has better crystallinity than those of amorphoussilicon, low-temperature polysilicon other than CGS and so on and isable to obtain higher mobility.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

1. A resistance-changing function body comprising: a first electrode; asecond electrode; a medium made of a first material interposed betweenthe first electrode and the second electrode; and at least oneconductive particle made of a third material, having a surface coveredwith a second material and included in the medium, wherein the secondmaterial has a barrier against passage of electric charges, the thirdmaterial has a capability to retain electric charges, and an electricalresistance between the first electrode and the second electrode ischanged depending on an amount of electric charges accumulated in theparticle.
 2. The resistance-changing function body as claimed in claim1, wherein the first material and the second material are mutuallydifferent insulative substances, the third material is a conductivematerial, and the second material is an insulative substance formed byusing the third material.
 3. A memory element comprising: a firstelectrode; a second electrode; and a memory function body interposedbetween the first electrode and the second electrode, wherein the memoryfunction body includes: a first insulator; and a conductive particleincluded in the first insulator and having a surface covered with amaterial having a barrier against passage of electric charges, andwherein a magnitude of a current through the memory function bodychanges by application of a prescribed voltage between the firstelectrode and the second electrode, and a storage state is discriminatedaccording to the magnitude of the current.
 4. A memory device comprisinga memory cell including: the memory element as claimed in claim 3; and arectifying function body having a rectification effect so as todetermine a direction of the current through the memory function body ofthe memory element, wherein the memory element and the rectifyingfunction body are electrically connected in series to each other.
 5. Amemory device comprising a memory cell including: the memory element asclaimed in claim 3; and a select transistor for selecting the memoryelement, wherein the memory element and the select transistor areelectrically connected in series to each other.
 6. A memory devicecomprising at least two memory cells each including the memory elementas claimed in claim 3, wherein the first insulators of the memoryfunction bodies of the two memory cells are integrally continuouslyformed, and the first electrode of one memory cell of the two memorycells and the first electrode of the other memory cell are electricallyconnected to each other, and the second electrode of the one memory celland the second electrode of the other memory cell are electricallyisolated from each other.
 7. A memory device comprising: at least fivememory cells each including the memory element as claimed in claim 3;bit lines extended in a direction of column; source lines extended in adirection of column; and word lines extended in a direction of row,wherein each of the memory cells includes: a select transistor forselecting the memory element; and a rectifying function body fordetermining a direction of the current through the memory function bodyof the memory element, and wherein each of the memory cells is connectedbetween the bit line and the source line, and the select transistor ofeach of the memory cells is controlled by the word line, with respect toa first memory cell of the five memory cells, a second and a fourthmemory cells are arranged mutually adjacently in the direction of row,and a third and a fifth memory cells are arranged mutually adjacently inthe direction of column, the first memory cell and the second memorycell have a shared bit line, a shared word line and an unshared sourceline, the first memory cell and the third memory cell have a shared bitline, a shared source line and an unshared word line, the first memorycell and the fourth memory cell have a shared source line, a shared wordline and an unshared bit line, the first memory cell and the fifthmemory cell have a shared word line, a source line of the first memorycell and a bit line of the fifth memory cell are shared, and a bit lineof the first memory cell and a source line of the fifth memory cell areshared.
 8. The memory device as claimed in claim 7, wherein at least twomemory cells are arranged in a direction parallel to a substrate, andthe first insulators of the memory function bodies of the memory cellsmutually adjacent in the direction parallel to the substrate areintegrally continuously formed.
 9. The memory device as claimed in claim7, wherein at least two memory cells are arranged in a directionparallel to a substrate, and the first insulators and/or the rectifyingfunction bodies of the memory cells mutually adjacent in the directionparallel to the substrate are integrally continuously formed.
 10. Thememory element as claimed in claim 3, further comprising a thirdelectrode adjacent to the memory function body, wherein the thirdelectrode is able to apply a voltage to the memory function body in aposition between the first electrode and the second electrode in adirection opposing the first electrode and the second electrode to eachother.
 11. The memory element as claimed in claim 10, wherein the firstelectrode and the second electrode are each formed on a surface of asemiconductor substrate, the memory function body is formed in a regionlocated between the electrodes on the surface of the semiconductorsubstrate, and the third electrode is provided on the memory functionbody.
 12. The memory element as claimed in claim 10, wherein the firstelectrode and the second electrode are each made of a conductor formedon a substrate, the memory function body is formed in a regioninterposed between the conductors, and the third electrode is providedon the memory function body.
 13. A memory device comprising: at leasttwo memory cells each including the memory element as claimed in claim3, wherein the memory cells are formed on a substrate, and the memoryfunction bodies of the memory cells are laminated in a directionperpendicular to the substrate.
 14. A method for manufacturing thememory element claimed in claim 3, comprising the step of: implanting asubstance for forming the conductive particle in the first insulator bya negative ion implantation method.
 15. A semiconductor devicecomprising the memory element claimed in claim
 3. 16. Electronicequipment comprising the semiconductor device claimed in claim 15.